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deinterlace: support VIU_FIELD interlace map from decode [1/1]

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PD#SWPL-22140

Problem:
DI don't support VIU_FIELD interlace map from decode

Solution:
Support it

Verify:
Verified on u212

Change-Id: Ibd34475881a36eb0891fd11fff091d4bbb233b50
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
This commit is contained in:
Brian Zhu
2020-03-13 11:25:42 +08:00
committed by Chris
parent 2213e5d17f
commit 35fd796cb5
3 changed files with 41 additions and 1 deletions
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34
drivers/amlogic/media/deinterlace/deinterlace.c
View File

@@ -3340,6 +3340,26 @@ static void config_di_mif(struct DI_MIF_s *di_mif, struct di_buf_s *di_buf)
di_mif->chroma_y_start0 = 0;
di_mif->chroma_y_end0 =
(di_buf->vframe->height + 1) / 2 - 1;
} else if ((di_buf->vframe->type & VIDTYPE_INTERLACE) &&
(di_buf->vframe->type & VIDTYPE_VIU_FIELD)) {
if (di_pre_stru.cur_inp_type & VIDTYPE_INTERLACE)
di_mif->src_prog = 0;
else
di_mif->src_prog = force_prog ? 1 : 0;
di_mif->src_field_mode = 0;
di_mif->output_field_num = 0; /* top */
di_mif->luma_x_start0 = 0;
di_mif->luma_x_end0 =
di_buf->vframe->width - 1;
di_mif->luma_y_start0 = 0;
di_mif->luma_y_end0 =
di_buf->vframe->height / 2 - 1;
di_mif->chroma_x_start0 = 0;
di_mif->chroma_x_end0 =
di_buf->vframe->width / 2 - 1;
di_mif->chroma_y_start0 = 0;
di_mif->chroma_y_end0 =
di_buf->vframe->height / 4 - 1;
} else {
if (di_pre_stru.cur_inp_type & VIDTYPE_INTERLACE)
di_mif->src_prog = 0;
@@ -3390,6 +3410,8 @@ static void di_pre_size_change(unsigned short width,
static void pre_inp_canvas_config(struct vframe_s *vf);
#endif
static void pre_inp_mif_w(struct DI_MIF_s *di_mif, struct vframe_s *vf);
bool secam_cfr_en = true;
unsigned int cfr_phase1 = 1;/*0x179c[6]*/
unsigned int cfr_phase2 = 1;/*0x179c[7]*/
@@ -3467,7 +3489,7 @@ static void pre_de_process(void)
#ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC
pre_inp_canvas_config(di_pre_stru.di_inp_buf->vframe);
#endif
pre_inp_mif_w(&di_pre_stru.di_inp_mif, di_pre_stru.di_inp_buf->vframe);
config_di_mif(&di_pre_stru.di_inp_mif, di_pre_stru.di_inp_buf);
/* pr_dbg("set_separate_en=%d vframe->type %d\n",
* di_pre_stru.di_inp_mif.set_separate_en,
@@ -4071,6 +4093,16 @@ static void pre_inp_canvas_config(struct vframe_s *vf)
}
}
#endif
static void pre_inp_mif_w(struct DI_MIF_s *di_mif, struct vframe_s *vf)
{
if (vf->canvas0Addr != (u32)-1)
di_mif->canvas_w = canvas_get_width(
vf->canvas0Addr & 0xff);
else
di_mif->canvas_w = vf->canvas0_config[0].width;
}
static int pps_dstw;
module_param_named(pps_dstw, pps_dstw, int, 0644);
static int pps_dsth;

6
drivers/amlogic/media/deinterlace/deinterlace_hw.c
View File

@@ -1560,6 +1560,7 @@ static void set_di_inp_mif(struct DI_MIF_s *mif, int urgent, int hold_line)
unsigned int chroma0_rpt_loop_pat;
unsigned int vt_ini_phase = 0;
unsigned int reset_on_gofield;
unsigned int burst_len = 2;
if (mif->set_separate_en != 0 && mif->src_field_mode == 1) {
chro_rpt_lastl_ctrl = 1;
@@ -1642,6 +1643,11 @@ static void set_di_inp_mif(struct DI_MIF_s *mif, int urgent, int hold_line)
RDMA_WR_BITS(DI_INP_GEN_REG2, 0, 0, 1);
}
if (mif->canvas_w % 32)
burst_len = 0;
else if (mif->canvas_w % 64)
burst_len = 1;
RDMA_WR_BITS(DI_INP_GEN_REG3, burst_len & 0x3, 1, 2);
RDMA_WR_BITS(DI_INP_GEN_REG3, mif->bit_mode&0x3, 8, 2);
RDMA_WR(DI_INP_CANVAS0, (mif->canvas0_addr2 << 16) |
/* cntl_canvas0_addr2 */

2
drivers/amlogic/media/deinterlace/deinterlace_hw.h
View File

@@ -79,6 +79,8 @@ struct DI_MIF_s {
unsigned canvas0_addr0:8;
unsigned canvas0_addr1:8;
unsigned canvas0_addr2:8;
/* canvas_w: for input not 64 align*/
unsigned int canvas_w;
};
struct DI_SIM_MIF_s {