usb: dwc3: add a quirk xhci_slow_suspend_quirk

On some xHCI controllers (e.g. Rockchip SoCs), which are
integrated in DWC3 IP, need an extraordinary delay to wait
for xHCI enter the Halted state(i.e. HCH in the USBSTS
register is '1'), especially if DWC3 is in DRD mode.

Change-Id: I7718a4052f67d40cddb50f7113dbb0b591746359
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This commit is contained in:
Wu Liang feng
2016-05-16 18:59:40 +08:00
parent 8bf2c6841d
commit 362400b861
5 changed files with 13 additions and 0 deletions

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@@ -45,6 +45,9 @@ Optional properties:
a free-running PHY clock.
- snps,dis_del_phy_power_chg_quirk: when set core will change PHY power
from P0 to P1/P2/P3 without delay.
- snps,xhci_slow_suspend_quirk: when set, need an extraordinary delay to wait
for xHC enter the Halted state (i.e. HCH in the USBSTS
register is '1').
- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
utmi_l1_suspend_n, false when asserts utmi_sleep_n
- snps,hird-threshold: HIRD threshold

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@@ -1024,6 +1024,8 @@ static int dwc3_probe(struct platform_device *pdev)
"snps,dis_u2_freeclk_exists_quirk");
dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
"snps,dis_del_phy_power_chg_quirk");
dwc->xhci_slow_suspend_quirk = device_property_read_bool(dev,
"snps,xhci_slow_suspend_quirk");
dwc->phyif_utmi_16_bits = device_property_read_bool(dev,
"snps,phyif_utmi_16_bits");
@@ -1064,6 +1066,8 @@ static int dwc3_probe(struct platform_device *pdev)
pdata->dis_u2_freeclk_exists_quirk;
dwc->dis_del_phy_power_chg_quirk =
pdata->dis_del_phy_power_chg_quirk;
dwc->xhci_slow_suspend_quirk =
pdata->xhci_slow_suspend_quirk;
dwc->phyif_utmi_16_bits = pdata->phyif_utmi_16_bits;
dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;

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@@ -748,6 +748,9 @@ struct dwc3_scratchpad_array {
* provide a free-running PHY clock.
* @dis_del_phy_power_chg_quirk: set if we disable delay phy power
* change quirk.
* @xhci_slow_suspend_quirk: set if need an extraordinary delay to wait
* for xHC enter the Halted state after the Run/Stop
* (R/S) bit is cleared to '0'.
* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
* @tx_de_emphasis: Tx de-emphasis value
* 0 - -6dB de-emphasis
@@ -897,6 +900,7 @@ struct dwc3 {
unsigned dis_enblslpm_quirk:1;
unsigned dis_u2_freeclk_exists_quirk:1;
unsigned dis_del_phy_power_chg_quirk:1;
unsigned xhci_slow_suspend_quirk:1;
unsigned tx_de_emphasis_quirk:1;
unsigned tx_de_emphasis:2;

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@@ -51,6 +51,7 @@ int dwc3_host_init(struct dwc3 *dwc)
memset(&pdata, 0, sizeof(pdata));
pdata.usb3_lpm_capable = dwc->usb3_lpm_capable;
pdata.xhci_slow_suspend = dwc->xhci_slow_suspend_quirk;
ret = platform_device_add_data(xhci, &pdata, sizeof(pdata));
if (ret) {

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@@ -46,6 +46,7 @@ struct dwc3_platform_data {
unsigned dis_enblslpm_quirk:1;
unsigned dis_u2_freeclk_exists_quirk:1;
unsigned dis_del_phy_power_chg_quirk:1;
unsigned xhci_slow_suspend_quirk:1;
unsigned tx_de_emphasis_quirk:1;
unsigned tx_de_emphasis:2;