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[ARM] tegra: fix packet alignment and padding

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tegra's DMA controller expects to start transfers at word boundaries,
and the standard packet alignment (2) was resulting in data corruption

also, provide a full cacheline of padding between skbuffs, to eliminate
coherency issues between the processor and USB networking devices.

Change-Id: Ibb508b512f43c8934d35eb182c8738370b7be585
Signed-off-by: Gary King <gking@nvidia.com>
This commit is contained in:
Gary King
2010-07-28 15:03:57 -07:00
committed by Colin Cross
parent 80a4c65c42
commit 367c3aab79
1 changed files with 3 additions and 0 deletions
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3
arch/arm/mach-tegra/include/mach/memory.h
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@@ -24,5 +24,8 @@
/* physical offset of RAM */
#define PHYS_OFFSET UL(0)
#define NET_IP_ALIGN 0
#define NET_SKB_PAD L1_CACHE_BYTES
#endif