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drm/rockchip: cdn-dp: enable/disable SSC based on the receiver capability

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Change-Id: Ie79fb55c6b315e252260f8593044e083a7a33e80
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2019-04-25 14:04:35 +08:00
committed by Tao Huang
parent b1fb40d126
commit 36ae4ef430
2 changed files with 18 additions and 2 deletions
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2
drivers/gpu/drm/rockchip/Kconfig
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@@ -32,7 +32,7 @@ config ROCKCHIP_DRM_DEBUG
config ROCKCHIP_CDN_DP
tristate "Rockchip cdn DP"
depends on DRM_ROCKCHIP
depends on DRM_ROCKCHIP && PHY_ROCKCHIP_TYPEC
select SND_SOC_HDMI_CODEC if SND_SOC
help
This selects support for Rockchip SoC specific extensions

18
drivers/gpu/drm/rockchip/cdn-dp-link-training.c
View File

@@ -360,9 +360,11 @@ static int cdn_dp_get_lower_link_rate(struct cdn_dp_device *dp)
int cdn_dp_software_train_link(struct cdn_dp_device *dp)
{
struct cdn_dp_port *port = dp->port[dp->active_port];
int ret, stop_err;
u8 link_config[2];
u32 rate, sink_max, source_max;
bool ssc_on;
ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd,
sizeof(dp->dpcd));
@@ -380,13 +382,27 @@ int cdn_dp_software_train_link(struct cdn_dp_device *dp)
rate = min(source_max, sink_max);
dp->link.rate = drm_dp_link_rate_to_bw_code(rate);
link_config[0] = 0;
ssc_on = !!(dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
link_config[0] = ssc_on ? DP_SPREAD_AMP_0_5 : 0;
link_config[1] = 0;
if (dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & 0x01)
link_config[1] = DP_SET_ANSI_8B10B;
drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
while (true) {
ret = tcphy_dp_set_link_rate(port->phy,
drm_dp_bw_code_to_link_rate(dp->link.rate),
ssc_on);
if (ret) {
DRM_ERROR("failed to set link rate: %d\n", ret);
return ret;
}
ret = tcphy_dp_set_lane_count(port->phy, dp->link.num_lanes);
if (ret) {
DRM_ERROR("failed to set lane count: %d\n", ret);
return ret;
}
/* Write the link configuration data */
link_config[0] = dp->link.rate;