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arm64: dts: rockchip: rk3568: modify cpu clk

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CPU clk using SCMI,replace <&cru ARMCLK> with <&scmi_clk 0>

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Change-Id: I321493604d95690ca2a2b4040dfcf8acd9f77697
This commit is contained in:
zhangqing
2020-12-22 14:45:07 +08:00
committed by Tao Huang
parent bd22b8ce75
commit 36f64d7150
1 changed files with 8 additions and 13 deletions
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21
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -61,7 +61,7 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
};
@@ -70,7 +70,7 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
};
@@ -79,7 +79,7 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
};
@@ -88,7 +88,7 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
clocks = <&scmi_clk 0>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
@@ -113,29 +113,24 @@
clock-latency-ns = <40000>;
opp-suspend;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <875000 875000 1150000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <925000 925000 1150000>;
opp-microvolt = <825000 825000 1150000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1025000 1025000 1150000>;
opp-microvolt = <900000 900000 1150000>;
clock-latency-ns = <40000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1100000 1100000 1150000>;
opp-microvolt = <975000 975000 1150000>;
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1100000 1100000 1150000>;
opp-microvolt = <1050000 1050000 1150000>;
clock-latency-ns = <40000>;
};
opp-1992000000 {