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clk: rockchip: px30: support px30s

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Change-Id: Id86199e066e254279d59a76aaed02f657b40e0c7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2021-08-10 11:16:34 +08:00
committed by Tao Huang
parent 365ee62df1
commit 3724dcef5f
2 changed files with 43 additions and 12 deletions
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52
drivers/clk/rockchip/clk-px30.c
View File

@@ -10,6 +10,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/rockchip/cpu.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/px30-cru.h>
#include "clk.h"
@@ -148,6 +149,7 @@ PNAME(mux_npll_cpll_p) = { "npll", "cpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
PNAME(mux_gpll_npll_p) = { "gpll", "dummy_npll" };
PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll"};
PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "dummy_npll" };
PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "dummy_npll", "xin24m" };
PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "dummy_npll"};
@@ -329,12 +331,6 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p,
CLK_IGNORE_UNUSED, PX30_CLKSEL_CON(2), 7, 1, 0, 3,
ROCKCHIP_DDRCLK_SIP_V2),
COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(0), 14, GFLAGS),
FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 4, 1, MFLAGS,
PX30_CLKGATE_CON(1), 13, GFLAGS),
@@ -761,12 +757,6 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
PX30_CLKSEL_CON(55), 0, 11, DFLAGS,
PX30_CLKGATE_CON(12), 10, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
PX30_CLKSEL_CON(56), 0, 3, DFLAGS,
PX30_CLKGATE_CON(12), 11, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
PX30_CLKSEL_CON(56), 4, 2, DFLAGS,
PX30_CLKGATE_CON(13), 6, GFLAGS),
GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(12), 12, GFLAGS),
@@ -983,6 +973,36 @@ static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
};
static struct rockchip_clk_branch px30_clk_ddrphy_otp[] __initdata = {
COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(0), 14, GFLAGS),
FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x",
CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
PX30_CLKSEL_CON(56), 0, 3, DFLAGS,
PX30_CLKGATE_CON(12), 11, GFLAGS),
COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
PX30_CLKSEL_CON(56), 4, 2, DFLAGS,
PX30_CLKGATE_CON(13), 6, GFLAGS),
};
static struct rockchip_clk_branch px30s_clk_ddrphy_otp[] __initdata = {
COMPOSITE(0, "clk_ddrphy1x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS,
PX30_CLKGATE_CON(0), 14, GFLAGS),
FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy1x",
CLK_IGNORE_UNUSED, 1, 4,
PX30_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE(SCLK_OTP_USR, "clk_otp_usr", mux_xin24m_gpll_p, 0,
PX30_CLKSEL_CON(56), 8, 1, MFLAGS, 0, 8, DFLAGS,
PX30_CLKGATE_CON(12), 11, GFLAGS),
};
static __initdata struct rockchip_clk_provider *cru_ctx, *pmucru_ctx;
static void __init px30_register_armclk(void)
{
@@ -1029,6 +1049,14 @@ static void __init px30_clk_init(struct device_node *np)
rockchip_clk_register_branches(ctx, rk3326_gpu_src_clk,
ARRAY_SIZE(rk3326_gpu_src_clk));
rockchip_soc_id_init();
if (soc_is_px30s())
rockchip_clk_register_branches(ctx, px30s_clk_ddrphy_otp,
ARRAY_SIZE(px30s_clk_ddrphy_otp));
else
rockchip_clk_register_branches(ctx, px30_clk_ddrphy_otp,
ARRAY_SIZE(px30_clk_ddrphy_otp));
rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);

3
include/dt-bindings/clock/px30-cru.h
View File

@@ -390,4 +390,7 @@
#define SRST_GRF_P 186
#define SRST_I2S0_RX 191
#define SRST_I2S0_RX_S 128
#define SRST_DCF_P_S 191
#endif