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mmc: rk_sdmmc: compatible with rk312x

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This commit is contained in:
lintao
2014-07-21 10:53:43 +08:00
parent a2d135a387
commit 38db72fe23
2 changed files with 14 additions and 18 deletions
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13
drivers/mmc/host/dw_mmc-rockchip.c
View File

@@ -84,6 +84,7 @@ enum dw_mci_rockchip_type {
DW_MCI_TYPE_RK3188,
DW_MCI_TYPE_RK3288,
DW_MCI_TYPE_RK3036,
DW_MCI_TYPE_RK312X,
};
/* Rockchip implementation specific driver private data */
@@ -108,6 +109,9 @@ static struct dw_mci_rockchip_compatible {
},{
.compatible = "rockchip,rk3036-sdmmc",
.ctrl_type = DW_MCI_TYPE_RK3036,
},{
.compatible = "rockchip,rk312x-sdmmc",
.ctrl_type = DW_MCI_TYPE_RK312X,
},
};
@@ -137,7 +141,8 @@ static int dw_mci_rockchip_setup_clock(struct dw_mci *host)
struct dw_mci_rockchip_priv_data *priv = host->priv;
if ((priv->ctrl_type == DW_MCI_TYPE_RK3288) ||
(priv->ctrl_type == DW_MCI_TYPE_RK3036))
(priv->ctrl_type == DW_MCI_TYPE_RK3036) ||
(priv->ctrl_type == DW_MCI_TYPE_RK312X))
host->bus_hz /= (priv->ciu_div + 1);
return 0;
@@ -270,11 +275,6 @@ static void dw_mci_rockchip_load_tuning_base(void)
/* load tuning base */
if(cpu_is_rk3288())
cru_tuning_base = RK3288_CRU_SDMMC_CON0;
/* Fixme: 3036
else if(cpu_is_rk3036())
cru_tuning_base = RK3036_CRU_SDMMC_CON0;
*/
}
static int inline __dw_mci_rockchip_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
@@ -359,7 +359,6 @@ static int dw_mci_rockchip_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
0.9 / 60ps = 15 delayline
*/
if(cpu_is_rk3288()){
/* Fixme: 3036: dose it compatitable? */
ref = ((FREQ_REF_150MHZ + host->bus_hz - 1) / host->bus_hz);
step = (15 * ref);

19
drivers/mmc/host/rk_sdmmc.c
View File

@@ -1827,12 +1827,9 @@ static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
struct dw_mci_tuning_data tuning_data;
int err = -ENOSYS;
/* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning
if(cpu_is_3036() || cpu_is_3126())
return ENOSYS;
AND
what about audi-b?
*/
/* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
if(cpu_is_rk3036() || cpu_is_rk312x())
return err;
if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
@@ -2848,7 +2845,7 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
#ifdef CONFIG_MMC_DW_IDMAC
/* External DMA Soc platform NOT need to ack interrupt IDSTS */
if(!cpu_is_rk3036()){
if(!(cpu_is_rk3036() || cpu_is_rk312x())){
/* Handle DMA interrupts */
pending = mci_readl(host, IDSTS);
if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
@@ -2941,7 +2938,7 @@ static void dw_mci_work_routine_card(struct work_struct *work)
/* Clear down the FIFO */
dw_mci_fifo_reset(host);
#ifdef CONFIG_MMC_DW_IDMAC
if(!cpu_is_rk3036())
if(!(cpu_is_rk3036() || cpu_is_rk312x()))
dw_mci_idmac_reset(host);
#endif
@@ -3247,7 +3244,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
mmc->max_blk_count = host->ring_size;
mmc->max_seg_size = 0x1000;
mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
if(cpu_is_rk3036()){
if(cpu_is_rk3036() || cpu_is_rk312x()){
/* fixup for external dmac setting */
mmc->max_segs = 64;
mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
@@ -3371,7 +3368,7 @@ static void dw_mci_init_dma(struct dw_mci *host)
/* Determine which DMA interface to use */
#if defined(CONFIG_MMC_DW_IDMAC)
if(cpu_is_rk3036()){
if(cpu_is_rk3036() || cpu_is_rk312x()){
host->dma_ops = &dw_mci_edmac_ops;
dev_info(host->dev, "Using external DMA controller.\n");
}else{
@@ -3564,7 +3561,7 @@ static void dw_mci_dealwith_timeout(struct dw_mci *host)
/* NO requirement to reclaim slave chn using external dmac */
#ifdef CONFIG_MMC_DW_IDMAC
if(!cpu_is_rk3036())
if(!(cpu_is_rk3036() || cpu_is_rk312x()))
if (host->use_dma && host->dma_ops->init)
host->dma_ops->init(host);
#endif