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arm64: dts: rockchip: add naneng combophy for rk3588

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Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ie4b56fb1a018d1ab0c9d4ee0cccaebde7703eaad
This commit is contained in:
Yifeng Zhao
2021-08-10 14:47:29 +08:00
committed by Tao Huang
parent 67d041d478
commit 39481cd6d3
2 changed files with 65 additions and 0 deletions
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20
arch/arm64/boot/dts/rockchip/rk3588.dtsi
View File

@@ -6,6 +6,11 @@
#include "rk3588s.dtsi"
/ {
pipe_phy1_grf: syscon@fd5c0000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfd5c0000 0x0 0x100>;
};
spdif_tx5: spdif-tx@fddb8000 {
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
reg = <0x0 0xfddb8000 0x0 0x1000>;
@@ -113,4 +118,19 @@
#sound-dai-cells = <0>;
status = "disabled";
};
combphy1_ps: phy@fee10000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee10000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>;
clock-names = "refclk", "apbclk";
assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
status = "disabled";
};
};

45
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -253,6 +253,21 @@
};
};
php_grf: syscon@fd5b0000 {
compatible = "rockchip,rk3588-php-grf", "syscon";
reg = <0x0 0xfd5b0000 0x0 0x1000>;
};
pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfd5bc000 0x0 0x100>;
};
pipe_phy2_grf: syscon@fd5c4000 {
compatible = "rockchip,pipe-phy-grf", "syscon";
reg = <0x0 0xfd5c4000 0x0 0x100>;
};
syssram: sram@fd600000 {
compatible = "mmio-sram";
reg = <0x0 0xfd600000 0x0 0x100000>;
@@ -1514,6 +1529,36 @@
arm,pl330-periph-burst;
};
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>;
clock-names = "refclk", "apbclk";
assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
status = "disabled";
};
combphy2_psu: phy@fee20000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee20000 0x0 0x100>;
#phy-cells = <1>;
clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>;
clock-names = "refclk", "apbclk";
assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>;
reset-names = "combphy-apb", "combphy";
rockchip,pipe-grf = <&php_grf>;
rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3588-pinctrl";
//rockchip,grf = <&grf>;