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arm64: dts: rockchip: add rv1126b-evb2-v10-dv

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Signed-off-by: Yu Zheng <yu.zheng@rock-chips.com>
Change-Id: I8ef95e04879741ccbf44573fe62020638beb8002
This commit is contained in:
Yu Zheng
2025-04-11 14:46:21 +08:00
committed by Tao Huang
parent 383d30e79b
commit 39a230accf
2 changed files with 92 additions and 0 deletions
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1
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -388,6 +388,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v11-dual-4k.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-aov-dual-cam.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-dv.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-mcu-k350c4516t.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-rgb-Q7050ITH2641AA1T.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-sii9022-bt1120-to-hdmi.dtb

91
arch/arm64/boot/dts/rockchip/rv1126b-evb2-v10-dv.dts Normal file
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@@ -0,0 +1,91 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1126b.dtsi"
#include "rv1126b-evb.dtsi"
#include "rv1126b-evb2-v10.dtsi"
#include "rv1126b-evb-cam-csi0.dtsi"
/ {
model = "Rockchip RV1126B EVB1 V10 DV Board";
compatible = "rockchip,rv1126b-evb2-v10-dv", "rockchip,rv1126b";
chosen {
bootargs = "earlycon=uart8250,mmio32,0x20810000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=32K isolcpus=3 nohz_full=3";
};
};
&gc8613 {
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>;
/delete-property/ pwdn-gpios;
};
&gpio5 {
interrupt-affinity = <&cpu0>, <&cpu0>, <&cpu0>, <&cpu3>;
interrupt-pins = <0>,
<0>,
<0>,
<RK_PIN_TO_BIT(RK_PB0)>;
};
&imx415 {
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
};
&imx586 {
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>;
};
&pinctrl {
inv {
inv_int1: inv-int1 {
rockchip,pins =
<5 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&rkfec {
status = "okay";
};
&rkfec_mmu {
status = "okay";
};
&rknpu {
status = "disabled";
};
&sc450ai {
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>;
};
&sc850sl {
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
};
&spi0 {
status = "okay";
max-freq = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&spi0m2_clk_pins &spi0m2_csn0_pins &inv_int1>;
icm42670: icm42670@0 {
compatible = "invensense,icm42670";
reg = <0x0>;
spi-max-frequency = <24000000>;
spi-cpha;
spi-cpol;
//vdd-supply = <&vcc_3v3_s0>;
int1-gpio = <&gpio5 RK_PB0 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&gpio5>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
};
};
&uart2 {
status = "disabled";
};