mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-08 20:07:46 +09:00
pinctrl: initial add pinmux
PD#138714: initial add pinmux and gpio Change-Id: I5154faab7508d066a302170fbb02b319413c8ea0 Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
This commit is contained in:
Jianxin Pan
@@ -7,6 +7,8 @@ Required properties for the root node:
|
||||
"amlogic,meson8b-aobus-pinctrl"
|
||||
"amlogic,meson-gxbb-periphs-pinctrl"
|
||||
"amlogic,meson-gxbb-aobus-pinctrl"
|
||||
"amlogic,meson-gxl-periphs-pinctrl"
|
||||
"amlogic,meson-gxl-aobus-pinctrl"
|
||||
- reg: address and size of registers controlling irq functionality
|
||||
|
||||
=== GPIO sub-nodes ===
|
||||
|
||||
@@ -13405,3 +13405,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
|
||||
S: Buried alive in reporters
|
||||
F: *
|
||||
F: */
|
||||
|
||||
AMLOGIC Pinmux
|
||||
M: Jianxin Pan <jianxin.pan@amlogic.com>
|
||||
F: drivers/amlogic/pinctrl/*
|
||||
|
||||
@@ -46,6 +46,61 @@
|
||||
reg = <0x0 0x10000000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
secos_reserved:linux,secos {
|
||||
status = "disable";
|
||||
compatible = "amlogic, aml_secos_memory";
|
||||
reg = <0x0 0x05300000 0x0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
pstore:aml_pstore {
|
||||
compatible = "amlogic, pstore";
|
||||
reg = <0x0 0x07300000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
fb_reserved:linux,meson-fb {
|
||||
compatible = "amlogic, fb-memory";
|
||||
size = <0x0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
di_reserved:linux,di {
|
||||
compatible = "amlogic, di-mem";
|
||||
size = <0x0 0x1e00000>; //10x1920x1088x3/2=30M
|
||||
//no-map;
|
||||
};
|
||||
|
||||
ion_reserved:linux,ion-dev {
|
||||
compatible = "amlogic, idev-mem";
|
||||
size = <0x0 0x2000000>;
|
||||
};
|
||||
|
||||
/* POST PROCESS MANAGER */
|
||||
ppmgr_reserved:linux,ppmgr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0x0 0x0>;
|
||||
};
|
||||
|
||||
codec_mm_cma:linux,codec_mm_cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0xc000000>;
|
||||
alignment = <0x0 0x400000>;
|
||||
linux,contiguous-region;
|
||||
};
|
||||
picdec_cma_reserved:linux,picdec {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x0>;
|
||||
alignment = <0x0 0x0>;
|
||||
linux,contiguous-region;
|
||||
};
|
||||
/* codec shared reserved */
|
||||
codec_mm_reserved:linux,codec_mm_reserved {
|
||||
compatible = "amlogic, codec-mm-reserved";
|
||||
size = <0x0 0x4100000>;
|
||||
alignment = <0x0 0x100000>;
|
||||
//no-map;
|
||||
};
|
||||
};
|
||||
|
||||
uart_AO: serial@c81004c0 {
|
||||
@@ -55,6 +110,8 @@
|
||||
status = "okay";
|
||||
xtal_tick_en = <1>;
|
||||
fifosize = < 64 >;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ao_uart_pins>;
|
||||
support-sysrq = <0>; /* 0 not support , 1 support */
|
||||
};
|
||||
};
|
||||
|
||||
@@ -46,6 +46,61 @@
|
||||
reg = <0x0 0x10000000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
secos_reserved:linux,secos {
|
||||
status = "disable";
|
||||
compatible = "amlogic, aml_secos_memory";
|
||||
reg = <0x0 0x05300000 0x0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
pstore:aml_pstore {
|
||||
compatible = "amlogic, pstore";
|
||||
reg = <0x0 0x07300000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
fb_reserved:linux,meson-fb {
|
||||
compatible = "amlogic, fb-memory";
|
||||
size = <0x0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
di_reserved:linux,di {
|
||||
compatible = "amlogic, di-mem";
|
||||
size = <0x0 0x1e00000>; //10x1920x1088x3/2=30M
|
||||
//no-map;
|
||||
};
|
||||
|
||||
ion_reserved:linux,ion-dev {
|
||||
compatible = "amlogic, idev-mem";
|
||||
size = <0x0 0x2000000>;
|
||||
};
|
||||
|
||||
/* POST PROCESS MANAGER */
|
||||
ppmgr_reserved:linux,ppmgr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0x0 0x0>;
|
||||
};
|
||||
|
||||
codec_mm_cma:linux,codec_mm_cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0xc000000>;
|
||||
alignment = <0x0 0x400000>;
|
||||
linux,contiguous-region;
|
||||
};
|
||||
picdec_cma_reserved:linux,picdec {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x0>;
|
||||
alignment = <0x0 0x0>;
|
||||
linux,contiguous-region;
|
||||
};
|
||||
/* codec shared reserved */
|
||||
codec_mm_reserved:linux,codec_mm_reserved {
|
||||
compatible = "amlogic, codec-mm-reserved";
|
||||
size = <0x0 0x4100000>;
|
||||
alignment = <0x0 0x100000>;
|
||||
//no-map;
|
||||
};
|
||||
};
|
||||
|
||||
uart_AO: serial@c81004c0 {
|
||||
@@ -55,6 +110,9 @@
|
||||
status = "okay";
|
||||
xtal_tick_en = <1>;
|
||||
fifosize = < 64 >;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ao_uart_pins>;
|
||||
support-sysrq = <0>; /* 0 not support , 1 support */
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
@@ -21,8 +21,8 @@
|
||||
#include "mesongxm.dtsi"
|
||||
/ {
|
||||
model = "Amlogic";
|
||||
compatible = "amlogic, Gxm";
|
||||
amlogic-dt-id = "gxm_q200_2g";
|
||||
compatible = "amlogic, Gxm";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
@@ -46,6 +46,56 @@
|
||||
reg = <0x0 0x10000000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
secos_reserved:linux,secos {
|
||||
status = "disable";
|
||||
compatible = "amlogic, aml_secos_memory";
|
||||
reg = <0x0 0x05300000 0x0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
pstore:aml_pstore {
|
||||
compatible = "amlogic, pstore";
|
||||
reg = <0x0 0x07300000 0x0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
di_reserved:linux,di {
|
||||
compatible = "amlogic, di-mem";
|
||||
size = <0x0 0x1e00000>; //10x1920x1088x3/2=30M
|
||||
//no-map;
|
||||
};
|
||||
|
||||
ion_reserved:linux,ion-dev {
|
||||
compatible = "amlogic, idev-mem";
|
||||
size = <0x0 0x4000000>;
|
||||
};
|
||||
|
||||
/* POST PROCESS MANAGER */
|
||||
ppmgr_reserved:linux,ppmgr {
|
||||
compatible = "amlogic, ppmgr_memory";
|
||||
size = <0x0 0x2000000>;
|
||||
};
|
||||
|
||||
codec_mm_cma:linux,codec_mm_cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0xd000000>;
|
||||
alignment = <0x0 0x400000>;
|
||||
linux,contiguous-region;
|
||||
};
|
||||
picdec_cma_reserved:linux,picdec {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0x0>;
|
||||
alignment = <0x0 0x0>;
|
||||
linux,contiguous-region;
|
||||
};
|
||||
/* codec shared reserved */
|
||||
codec_mm_reserved:linux,codec_mm_reserved {
|
||||
compatible = "amlogic, codec-mm-reserved";
|
||||
size = <0x0 0x4100000>;
|
||||
alignment = <0x0 0x100000>;
|
||||
//no-map;
|
||||
};
|
||||
};
|
||||
|
||||
uart_AO: serial@c81004c0 {
|
||||
@@ -55,6 +105,9 @@
|
||||
status = "okay";
|
||||
xtal_tick_en = <1>;
|
||||
fifosize = < 64 >;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ao_uart_pins>;
|
||||
support-sysrq = <0>; /* 0 not support , 1 support */
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
@@ -32,7 +32,7 @@
|
||||
|
||||
memory@00000000 {
|
||||
device_type = "memory";
|
||||
linux,usable-memory = <0x0 0x1000000 0x0 0x3f000000>;
|
||||
linux,usable-memory = <0x0 0x100000 0x0 0x3ff00000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
|
||||
@@ -164,4 +164,429 @@
|
||||
cpu_version{
|
||||
reg=<0x0 0xc8100220 0x0 0x4>;
|
||||
};
|
||||
aobus: aobus@c8100000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xc8100000 0x0 0x100000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
|
||||
|
||||
pinctrl_aobus: pinctrl@14 {
|
||||
compatible = "amlogic,meson-gxl-aobus-pinctrl";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio_ao: bank@14 {
|
||||
reg = <0x0 0x00014 0x0 0x8>,
|
||||
<0x0 0x0002c 0x0 0x4>,
|
||||
<0x0 0x00024 0x0 0x8>;
|
||||
reg-names = "mux", "pull", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
|
||||
remote_pins:remote_pin {
|
||||
mux {
|
||||
groups = "remote_input";
|
||||
function = "remote";
|
||||
};
|
||||
};
|
||||
|
||||
ao_uart_pins:ao_uart {
|
||||
mux {
|
||||
groups = "uart_tx_ao_a_0",
|
||||
"uart_rx_ao_a_0";
|
||||
function = "uart_ao";
|
||||
};
|
||||
};
|
||||
|
||||
ao_b_uart_pins:ao_b_uart {
|
||||
mux {
|
||||
groups = "uart_tx_ao_b_0",
|
||||
"uart_rx_ao_b_0";
|
||||
function = "uart_ao_b";
|
||||
};
|
||||
};
|
||||
|
||||
hdmitx_aocec: hdmitx_aocec {
|
||||
mux {
|
||||
groups = "ao_cec";
|
||||
function = "ao_cec";
|
||||
};
|
||||
};
|
||||
|
||||
hdmitx_eecec: hdmitx_eecec {
|
||||
mux {
|
||||
groups = "ee_cec";
|
||||
function = "ee_cec";
|
||||
};
|
||||
};
|
||||
}; /* end of pinctrl_aobus*/
|
||||
|
||||
}; /* end of aobus*/
|
||||
|
||||
periphs: periphs@c8834000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xc8834000 0x0 0x2000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
|
||||
|
||||
rng {
|
||||
compatible = "amlogic,meson-rng";
|
||||
reg = <0x0 0x0 0x0 0x4>;
|
||||
};
|
||||
|
||||
pinctrl_periphs: pinctrl@4b0 {
|
||||
compatible = "amlogic,meson-gxl-periphs-pinctrl";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio: bank@4b0 {
|
||||
reg = <0x0 0x004b0 0x0 0x28>,
|
||||
<0x0 0x004e8 0x0 0x14>,
|
||||
<0x0 0x00120 0x0 0x14>,
|
||||
<0x0 0x00430 0x0 0x40>;
|
||||
reg-names = "mux", "pull",
|
||||
"pull-enable", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
eth_pins:eth_pins {
|
||||
mux {
|
||||
groups = "eth_mdio",
|
||||
"eth_mdc",
|
||||
"eth_clk_rx_clk",
|
||||
"eth_rx_dv",
|
||||
"eth_rxd0",
|
||||
"eth_rxd1",
|
||||
"eth_rxd2",
|
||||
"eth_rxd3",
|
||||
"eth_rgmii_tx_clk",
|
||||
"eth_tx_en",
|
||||
"eth_txd0",
|
||||
"eth_txd1",
|
||||
"eth_txd2",
|
||||
"eth_txd3";
|
||||
function = "eth";
|
||||
};
|
||||
};
|
||||
|
||||
jtag_apao_pins:jtag_apao_pin {
|
||||
mux {
|
||||
groups = "jtag_tdi_0",
|
||||
"jtag_tdo_0",
|
||||
"jtag_clk_0",
|
||||
"jtag_tms_0";
|
||||
function = "jtag";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
jtag_apee_pins:jtag_apee_pin {
|
||||
mux {
|
||||
groups ="jtag_tdi_1",
|
||||
"jtag_tdo_1",
|
||||
"jtag_clk_1",
|
||||
"jtag_tms_1";
|
||||
function = "jtag";
|
||||
};
|
||||
};
|
||||
|
||||
a_uart_pins:a_uart {
|
||||
mux {
|
||||
groups = "uart_tx_a",
|
||||
"uart_rx_a";
|
||||
function = "uart_a";
|
||||
};
|
||||
};
|
||||
|
||||
b_uart_pins:b_uart {
|
||||
mux {
|
||||
groups = "uart_tx_b",
|
||||
"uart_rx_b";
|
||||
function = "uart_b";
|
||||
};
|
||||
};
|
||||
|
||||
c_uart_pins:c_uart {
|
||||
mux {
|
||||
groups = "uart_tx_c",
|
||||
"uart_rx_c";
|
||||
function = "uart_c";
|
||||
};
|
||||
};
|
||||
|
||||
wifi_32k_pins:wifi_32k_pins {
|
||||
mux {
|
||||
groups ="pwm_e";
|
||||
function = "pwm_e";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* sd_clk_cmd_pins:sd_clk_cmd_pins{
|
||||
* };
|
||||
* sd_all_pins:sd_all_pins {
|
||||
* };
|
||||
* sd_1bit_pins:sd_1bit_pins{
|
||||
* };
|
||||
* sd_clk_cmd_uart_pins:sd_clk_cmd_uart_pins {
|
||||
* };
|
||||
* sd_1bit_uart_pins:sd_1bit_uart_pins {
|
||||
* };
|
||||
* sd_to_ao_uart_pins:sd_to_ao_uart_pins {
|
||||
* };
|
||||
* ao_to_sd_uart_pins:ao_to_sd_uart_pins {
|
||||
* };
|
||||
* sd_to_ao_jtag_pins:sd_to_ao_jtag_pins{
|
||||
* };
|
||||
*/
|
||||
|
||||
emmc_clk_cmd_pins:emmc_clk_cmd_pins {
|
||||
mux {
|
||||
groups = "emmc_cmd",
|
||||
"emmc_clk";
|
||||
function = "emmc";
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
emmc_pins: emmc {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"emmc_cmd",
|
||||
"emmc_clk";
|
||||
function = "emmc";
|
||||
};
|
||||
};
|
||||
|
||||
emmc_conf_pull_up:emmc_conf_pull_up {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"emmc_clk",
|
||||
"emmc_cmd";
|
||||
function = "emmc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
emmc_conf_pull_done:emmc_conf_pull_done {
|
||||
mux {
|
||||
groups = "emmc_ds";
|
||||
function = "emmc";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
emmc_all_pins:emmc_all_pins {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"emmc_clk",
|
||||
"emmc_cmd";
|
||||
function = "emmc";
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_clk_cmd_pins:sdio_clk_cmd_pins {
|
||||
mux {
|
||||
groups = "sdio_clk",
|
||||
"sdio_cmd";
|
||||
function = "sdio";
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_all_pins:sdio_all_pins {
|
||||
mux {
|
||||
groups = "sdio_d0",
|
||||
"sdio_d1",
|
||||
"sdio_d2",
|
||||
"sdio_d3",
|
||||
"sdio_clk",
|
||||
"sdio_cmd";
|
||||
function = "sdio";
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
conf_nand_pulldown: conf_nand_pulldown {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"emmc_ds";
|
||||
function = "emmc";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
conf_nand_pullup: conf_nand_pullup {
|
||||
mux {
|
||||
groups = "emmc_clk",
|
||||
"emmc_cmd";
|
||||
function = "emmc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
all_nand_pins: all_nand_pins {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"nand_ce0",
|
||||
"nand_ce1",
|
||||
"nand_rb0",
|
||||
"nand_ale",
|
||||
"nand_cle",
|
||||
"nand_wen_clk",
|
||||
"nand_ren_wr",
|
||||
"nand_dqs";
|
||||
function = "nand";
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_cs_pins: nand_cs {
|
||||
mux {
|
||||
groups = "nand_ce0",
|
||||
"nand_ce1";
|
||||
function = "nand";
|
||||
};
|
||||
};
|
||||
|
||||
hdmitx_hpd: hdmitx_hpd {
|
||||
mux {
|
||||
groups = "hdmi_hpd";
|
||||
function = "hdmi_hpd";
|
||||
};
|
||||
};
|
||||
|
||||
hdmitx_ddc: hdmitx_ddc {
|
||||
mux {
|
||||
groups = "hdmi_sda",
|
||||
"hdmi_scl";
|
||||
function = "hdmi_ddc";
|
||||
};
|
||||
};
|
||||
|
||||
a_i2c_master:a_i2c {
|
||||
mux {
|
||||
groups = "i2c_sda_a",
|
||||
"i2c_sda_a";
|
||||
function = "i2c_a";
|
||||
};
|
||||
};
|
||||
|
||||
b_i2c_master:b_i2c {
|
||||
mux {
|
||||
groups = "i2c_sda_b",
|
||||
"i2c_sda_b";
|
||||
function = "i2c_b";
|
||||
};
|
||||
};
|
||||
|
||||
c_i2c_master:c_i2c {
|
||||
mux {
|
||||
groups = "i2c_sda_c",
|
||||
"i2c_sda_c";
|
||||
function = "i2c_c";
|
||||
};
|
||||
};
|
||||
|
||||
d_i2c_master:d_i2c {
|
||||
mux {
|
||||
groups = "i2c_sda_d",
|
||||
"i2c_sda_d";
|
||||
function = "i2c_d";
|
||||
};
|
||||
};
|
||||
|
||||
spicc_pins_z11z12z13: spicc_pins_z11z12z13 {
|
||||
mux {
|
||||
groups = "spi_sclk_0",
|
||||
"spi_miso_0",
|
||||
"spi_mosi_0";
|
||||
function = "spi";
|
||||
};
|
||||
};
|
||||
spicc_pulldown_z11z12z13: spicc_pulldown_z11z12z13 {
|
||||
mux {
|
||||
groups = "spi_sclk_0",
|
||||
"spi_miso_0",
|
||||
"spi_mosi_0";
|
||||
function = "spi";
|
||||
};
|
||||
};
|
||||
|
||||
spicc_pullup_z11z12z13: spicc_pullup_z11z12z13 {
|
||||
mux {
|
||||
groups = "spi_sclk_0",
|
||||
"spi_miso_0",
|
||||
"spi_mosi_0";
|
||||
function = "spi";
|
||||
};
|
||||
};
|
||||
|
||||
spicc_pins_x8x9x11: spicc_pins_x8x9x11 {
|
||||
mux {
|
||||
groups = "spi_sclk_1",
|
||||
"spi_miso_1",
|
||||
"spi_mosi_1";
|
||||
function = "spi";
|
||||
};
|
||||
};
|
||||
spicc_pulldown_x8x9x11: spicc_pulldown_x8x9x11 {
|
||||
mux {
|
||||
groups = "spi_sclk_1",
|
||||
"spi_miso_1",
|
||||
"spi_mosi_1";
|
||||
function = "spi";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
spicc_pullup_x8x9x11: spicc_pullup_x8x9x11 {
|
||||
mux {
|
||||
groups = "spi_sclk_1",
|
||||
"spi_miso_1",
|
||||
"spi_mosi_1";
|
||||
function = "spi";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
audio_pins:audio_pin {
|
||||
mux {
|
||||
groups = "i2s_am_clk",
|
||||
"i2s_ao_clk_out",
|
||||
"i2s_lr_clk_out",
|
||||
"i2sout_ch01";
|
||||
function = "i2s";
|
||||
};
|
||||
};
|
||||
|
||||
audio_spdif_pins:audio_pin1 {
|
||||
mux {
|
||||
groups = "spdif_out";
|
||||
function = "spdif_out";
|
||||
};
|
||||
};
|
||||
|
||||
audio_btpcm_pins:audio_btpcm_pins {
|
||||
mux {
|
||||
groups = "pcm_out_a",
|
||||
"pcm_in_a",
|
||||
"pcm_fs_a",
|
||||
"pcm_clk_a";
|
||||
function = "pcm_a";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};/* end of / */
|
||||
|
||||
@@ -209,4 +209,429 @@
|
||||
cpu_version{
|
||||
reg=<0x0 0xc8100220 0x0 0x4>;
|
||||
};
|
||||
aobus: aobus@c8100000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xc8100000 0x0 0x100000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
|
||||
|
||||
pinctrl_aobus: pinctrl@14 {
|
||||
compatible = "amlogic,meson-gxl-aobus-pinctrl";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio_ao: bank@14 {
|
||||
reg = <0x0 0x00014 0x0 0x8>,
|
||||
<0x0 0x0002c 0x0 0x4>,
|
||||
<0x0 0x00024 0x0 0x8>;
|
||||
reg-names = "mux", "pull", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
|
||||
remote_pins:remote_pin {
|
||||
mux {
|
||||
groups = "remote_input";
|
||||
function = "remote";
|
||||
};
|
||||
};
|
||||
|
||||
ao_uart_pins:ao_uart {
|
||||
mux {
|
||||
groups = "uart_tx_ao_a_0",
|
||||
"uart_rx_ao_a_0";
|
||||
function = "uart_ao";
|
||||
};
|
||||
};
|
||||
|
||||
ao_b_uart_pins:ao_b_uart {
|
||||
mux {
|
||||
groups = "uart_tx_ao_b_0",
|
||||
"uart_rx_ao_b_0";
|
||||
function = "uart_ao_b";
|
||||
};
|
||||
};
|
||||
|
||||
hdmitx_aocec: hdmitx_aocec {
|
||||
mux {
|
||||
groups = "ao_cec";
|
||||
function = "ao_cec";
|
||||
};
|
||||
};
|
||||
|
||||
hdmitx_eecec: hdmitx_eecec {
|
||||
mux {
|
||||
groups = "ee_cec";
|
||||
function = "ee_cec";
|
||||
};
|
||||
};
|
||||
}; /* end of pinctrl_aobus*/
|
||||
|
||||
}; /* end of aobus*/
|
||||
|
||||
periphs: periphs@c8834000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xc8834000 0x0 0x2000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
|
||||
|
||||
rng {
|
||||
compatible = "amlogic,meson-rng";
|
||||
reg = <0x0 0x0 0x0 0x4>;
|
||||
};
|
||||
|
||||
pinctrl_periphs: pinctrl@4b0 {
|
||||
compatible = "amlogic,meson-gxl-periphs-pinctrl";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gpio: bank@4b0 {
|
||||
reg = <0x0 0x004b0 0x0 0x28>,
|
||||
<0x0 0x004e8 0x0 0x14>,
|
||||
<0x0 0x00120 0x0 0x14>,
|
||||
<0x0 0x00430 0x0 0x40>;
|
||||
reg-names = "mux", "pull",
|
||||
"pull-enable", "gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
eth_pins:eth_pins {
|
||||
mux {
|
||||
groups = "eth_mdio",
|
||||
"eth_mdc",
|
||||
"eth_clk_rx_clk",
|
||||
"eth_rx_dv",
|
||||
"eth_rxd0",
|
||||
"eth_rxd1",
|
||||
"eth_rxd2",
|
||||
"eth_rxd3",
|
||||
"eth_rgmii_tx_clk",
|
||||
"eth_tx_en",
|
||||
"eth_txd0",
|
||||
"eth_txd1",
|
||||
"eth_txd2",
|
||||
"eth_txd3";
|
||||
function = "eth";
|
||||
};
|
||||
};
|
||||
|
||||
jtag_apao_pins:jtag_apao_pin {
|
||||
mux {
|
||||
groups = "jtag_tdi_0",
|
||||
"jtag_tdo_0",
|
||||
"jtag_clk_0",
|
||||
"jtag_tms_0";
|
||||
function = "jtag";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
jtag_apee_pins:jtag_apee_pin {
|
||||
mux {
|
||||
groups ="jtag_tdi_1",
|
||||
"jtag_tdo_1",
|
||||
"jtag_clk_1",
|
||||
"jtag_tms_1";
|
||||
function = "jtag";
|
||||
};
|
||||
};
|
||||
|
||||
a_uart_pins:a_uart {
|
||||
mux {
|
||||
groups = "uart_tx_a",
|
||||
"uart_rx_a";
|
||||
function = "uart_a";
|
||||
};
|
||||
};
|
||||
|
||||
b_uart_pins:b_uart {
|
||||
mux {
|
||||
groups = "uart_tx_b",
|
||||
"uart_rx_b";
|
||||
function = "uart_b";
|
||||
};
|
||||
};
|
||||
|
||||
c_uart_pins:c_uart {
|
||||
mux {
|
||||
groups = "uart_tx_c",
|
||||
"uart_rx_c";
|
||||
function = "uart_c";
|
||||
};
|
||||
};
|
||||
|
||||
wifi_32k_pins:wifi_32k_pins {
|
||||
mux {
|
||||
groups ="pwm_e";
|
||||
function = "pwm_e";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* sd_clk_cmd_pins:sd_clk_cmd_pins{
|
||||
* };
|
||||
* sd_all_pins:sd_all_pins {
|
||||
* };
|
||||
* sd_1bit_pins:sd_1bit_pins{
|
||||
* };
|
||||
* sd_clk_cmd_uart_pins:sd_clk_cmd_uart_pins {
|
||||
* };
|
||||
* sd_1bit_uart_pins:sd_1bit_uart_pins {
|
||||
* };
|
||||
* sd_to_ao_uart_pins:sd_to_ao_uart_pins {
|
||||
* };
|
||||
* ao_to_sd_uart_pins:ao_to_sd_uart_pins {
|
||||
* };
|
||||
* sd_to_ao_jtag_pins:sd_to_ao_jtag_pins{
|
||||
* };
|
||||
*/
|
||||
|
||||
emmc_clk_cmd_pins:emmc_clk_cmd_pins {
|
||||
mux {
|
||||
groups = "emmc_cmd",
|
||||
"emmc_clk";
|
||||
function = "emmc";
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
emmc_pins: emmc {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"emmc_cmd",
|
||||
"emmc_clk";
|
||||
function = "emmc";
|
||||
};
|
||||
};
|
||||
|
||||
emmc_conf_pull_up:emmc_conf_pull_up {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"emmc_clk",
|
||||
"emmc_cmd";
|
||||
function = "emmc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
emmc_conf_pull_done:emmc_conf_pull_done {
|
||||
mux {
|
||||
groups = "emmc_ds";
|
||||
function = "emmc";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
emmc_all_pins:emmc_all_pins {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"emmc_clk",
|
||||
"emmc_cmd";
|
||||
function = "emmc";
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_clk_cmd_pins:sdio_clk_cmd_pins {
|
||||
mux {
|
||||
groups = "sdio_clk",
|
||||
"sdio_cmd";
|
||||
function = "sdio";
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_all_pins:sdio_all_pins {
|
||||
mux {
|
||||
groups = "sdio_d0",
|
||||
"sdio_d1",
|
||||
"sdio_d2",
|
||||
"sdio_d3",
|
||||
"sdio_clk",
|
||||
"sdio_cmd";
|
||||
function = "sdio";
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
conf_nand_pulldown: conf_nand_pulldown {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"emmc_ds";
|
||||
function = "emmc";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
conf_nand_pullup: conf_nand_pullup {
|
||||
mux {
|
||||
groups = "emmc_clk",
|
||||
"emmc_cmd";
|
||||
function = "emmc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
all_nand_pins: all_nand_pins {
|
||||
mux {
|
||||
groups = "emmc_nand_d07",
|
||||
"nand_ce0",
|
||||
"nand_ce1",
|
||||
"nand_rb0",
|
||||
"nand_ale",
|
||||
"nand_cle",
|
||||
"nand_wen_clk",
|
||||
"nand_ren_wr",
|
||||
"nand_dqs";
|
||||
function = "nand";
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_cs_pins: nand_cs {
|
||||
mux {
|
||||
groups = "nand_ce0",
|
||||
"nand_ce1";
|
||||
function = "nand";
|
||||
};
|
||||
};
|
||||
|
||||
hdmitx_hpd: hdmitx_hpd {
|
||||
mux {
|
||||
groups = "hdmi_hpd";
|
||||
function = "hdmi_hpd";
|
||||
};
|
||||
};
|
||||
|
||||
hdmitx_ddc: hdmitx_ddc {
|
||||
mux {
|
||||
groups = "hdmi_sda",
|
||||
"hdmi_scl";
|
||||
function = "hdmi_ddc";
|
||||
};
|
||||
};
|
||||
|
||||
a_i2c_master:a_i2c {
|
||||
mux {
|
||||
groups = "i2c_sda_a",
|
||||
"i2c_sda_a";
|
||||
function = "i2c_a";
|
||||
};
|
||||
};
|
||||
|
||||
b_i2c_master:b_i2c {
|
||||
mux {
|
||||
groups = "i2c_sda_b",
|
||||
"i2c_sda_b";
|
||||
function = "i2c_b";
|
||||
};
|
||||
};
|
||||
|
||||
c_i2c_master:c_i2c {
|
||||
mux {
|
||||
groups = "i2c_sda_c",
|
||||
"i2c_sda_c";
|
||||
function = "i2c_c";
|
||||
};
|
||||
};
|
||||
|
||||
d_i2c_master:d_i2c {
|
||||
mux {
|
||||
groups = "i2c_sda_d",
|
||||
"i2c_sda_d";
|
||||
function = "i2c_d";
|
||||
};
|
||||
};
|
||||
|
||||
spicc_pins_z11z12z13: spicc_pins_z11z12z13 {
|
||||
mux {
|
||||
groups = "spi_sclk_0",
|
||||
"spi_miso_0",
|
||||
"spi_mosi_0";
|
||||
function = "spi";
|
||||
};
|
||||
};
|
||||
spicc_pulldown_z11z12z13: spicc_pulldown_z11z12z13 {
|
||||
mux {
|
||||
groups = "spi_sclk_0",
|
||||
"spi_miso_0",
|
||||
"spi_mosi_0";
|
||||
function = "spi";
|
||||
};
|
||||
};
|
||||
|
||||
spicc_pullup_z11z12z13: spicc_pullup_z11z12z13 {
|
||||
mux {
|
||||
groups = "spi_sclk_0",
|
||||
"spi_miso_0",
|
||||
"spi_mosi_0";
|
||||
function = "spi";
|
||||
};
|
||||
};
|
||||
|
||||
spicc_pins_x8x9x11: spicc_pins_x8x9x11 {
|
||||
mux {
|
||||
groups = "spi_sclk_1",
|
||||
"spi_miso_1",
|
||||
"spi_mosi_1";
|
||||
function = "spi";
|
||||
};
|
||||
};
|
||||
spicc_pulldown_x8x9x11: spicc_pulldown_x8x9x11 {
|
||||
mux {
|
||||
groups = "spi_sclk_1",
|
||||
"spi_miso_1",
|
||||
"spi_mosi_1";
|
||||
function = "spi";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
spicc_pullup_x8x9x11: spicc_pullup_x8x9x11 {
|
||||
mux {
|
||||
groups = "spi_sclk_1",
|
||||
"spi_miso_1",
|
||||
"spi_mosi_1";
|
||||
function = "spi";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
audio_pins:audio_pin {
|
||||
mux {
|
||||
groups = "i2s_am_clk",
|
||||
"i2s_ao_clk_out",
|
||||
"i2s_lr_clk_out",
|
||||
"i2sout_ch01";
|
||||
function = "i2s";
|
||||
};
|
||||
};
|
||||
|
||||
audio_spdif_pins:audio_pin1 {
|
||||
mux {
|
||||
groups = "spdif_out";
|
||||
function = "spdif_out";
|
||||
};
|
||||
};
|
||||
|
||||
audio_btpcm_pins:audio_btpcm_pins {
|
||||
mux {
|
||||
groups = "pcm_out_a",
|
||||
"pcm_in_a",
|
||||
"pcm_fs_a",
|
||||
"pcm_clk_a";
|
||||
function = "pcm_a";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};/* end of / */
|
||||
|
||||
@@ -157,6 +157,7 @@ CONFIG_AMLOGIC_DRIVER=y
|
||||
CONFIG_AMLOGIC_UART=y
|
||||
CONFIG_AMLOGIC_SERIAL_MESON_CONSOLE=y
|
||||
CONFIG_AMLOGIC_IOMAP=y
|
||||
CONFIG_AMLOGIC_PINCTRL=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
@@ -305,3 +306,4 @@ CONFIG_CRYPTO_USER_API_HASH=y
|
||||
CONFIG_CRYPTO_USER_API_SKCIPHER=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRC7=y
|
||||
|
||||
|
||||
@@ -15,5 +15,6 @@ source "drivers/amlogic/uart/Kconfig"
|
||||
|
||||
source "drivers/amlogic/iomap/Kconfig"
|
||||
|
||||
source "drivers/amlogic/pinctrl/Kconfig"
|
||||
endmenu
|
||||
endif
|
||||
|
||||
@@ -10,4 +10,5 @@
|
||||
|
||||
obj-$(CONFIG_AMLOGIC_UART) += uart/
|
||||
|
||||
obj-$(CONFIG_AMLOGIC_PINCTRL) += pinctrl/
|
||||
obj-$(CONFIG_AMLOGIC_IOMAP) += iomap/
|
||||
|
||||
14
drivers/amlogic/pinctrl/Kconfig
Normal file
14
drivers/amlogic/pinctrl/Kconfig
Normal file
@@ -0,0 +1,14 @@
|
||||
# Amlogic PINCTRL
|
||||
|
||||
|
||||
config AMLOGIC_PINCTRL
|
||||
bool "PINCTRL/GPIO support"
|
||||
select OF
|
||||
select PINCTRL
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select GPIOLIB
|
||||
select OF_GPIO
|
||||
help
|
||||
This is the Amlogic PINCTRL/GPIO driver
|
||||
4
drivers/amlogic/pinctrl/Makefile
Normal file
4
drivers/amlogic/pinctrl/Makefile
Normal file
@@ -0,0 +1,4 @@
|
||||
#
|
||||
#Makefile for the gpio dirver
|
||||
#
|
||||
obj-$(CONFIG_AMLOGIC_PINCTRL) += pinctrl-meson.o pinctrl_gxl.o
|
||||
760
drivers/amlogic/pinctrl/pinctrl-meson.c
Normal file
760
drivers/amlogic/pinctrl/pinctrl-meson.c
Normal file
@@ -0,0 +1,760 @@
|
||||
/*
|
||||
* drivers/amlogic/pinctrl/pinctrl-meson.c
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
|
||||
* BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
|
||||
* X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
|
||||
* variable number of pins.
|
||||
*
|
||||
* The AO bank is special because it belongs to the Always-On power
|
||||
* domain which can't be powered off; the bank also uses a set of
|
||||
* registers different from the other banks.
|
||||
*
|
||||
* For each of the two power domains (regular and always-on) there are
|
||||
* 4 different register ranges that control the following properties
|
||||
* of the pins:
|
||||
* 1) pin muxing
|
||||
* 2) pull enable/disable
|
||||
* 3) pull up/down
|
||||
* 4) GPIO direction, output value, input value
|
||||
*
|
||||
* In some cases the register ranges for pull enable and pull
|
||||
* direction are the same and thus there are only 3 register ranges.
|
||||
*
|
||||
* Every pinmux group can be enabled by a specific bit in the first
|
||||
* register range of the domain; when all groups for a given pin are
|
||||
* disabled the pin acts as a GPIO.
|
||||
*
|
||||
* For the pull and GPIO configuration every bank uses a contiguous
|
||||
* set of bits in the register sets described above; the same register
|
||||
* can be shared by more banks with different offsets.
|
||||
*
|
||||
* In addition to this there are some registers shared between all
|
||||
* banks that control the IRQ functionality. This feature is not
|
||||
* supported at the moment by the driver.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/pinctrl/pinconf.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
#include <linux/module.h>
|
||||
#include "../../pinctrl/core.h"
|
||||
#include "../../pinctrl/pinctrl-utils.h"
|
||||
#include "pinctrl-meson.h"
|
||||
|
||||
/**
|
||||
* meson_get_bank() - find the bank containing a given pin
|
||||
*
|
||||
* @domain: the domain containing the pin
|
||||
* @pin: the pin number
|
||||
* @bank: the found bank
|
||||
*
|
||||
* Return: 0 on success, a negative value on error
|
||||
*/
|
||||
static int meson_get_bank(struct meson_domain *domain, unsigned int pin,
|
||||
struct meson_bank **bank)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < domain->data->num_banks; i++) {
|
||||
if (pin >= domain->data->banks[i].first &&
|
||||
pin <= domain->data->banks[i].last) {
|
||||
*bank = &domain->data->banks[i];
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* meson_get_domain_and_bank() - find domain and bank containing a given pin
|
||||
*
|
||||
* @pc: Meson pin controller device
|
||||
* @pin: the pin number
|
||||
* @domain: the found domain
|
||||
* @bank: the found bank
|
||||
*
|
||||
* Return: 0 on success, a negative value on error
|
||||
*/
|
||||
static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin,
|
||||
struct meson_domain **domain,
|
||||
struct meson_bank **bank)
|
||||
{
|
||||
struct meson_domain *d;
|
||||
|
||||
d = pc->domain;
|
||||
|
||||
if (pin >= d->data->pin_base &&
|
||||
pin < d->data->pin_base + d->data->num_pins) {
|
||||
*domain = d;
|
||||
return meson_get_bank(d, pin, bank);
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* meson_calc_reg_and_bit() - calculate register and bit for a pin
|
||||
*
|
||||
* @bank: the bank containing the pin
|
||||
* @pin: the pin number
|
||||
* @reg_type: the type of register needed (pull-enable, pull, etc...)
|
||||
* @reg: the computed register offset
|
||||
* @bit: the computed bit
|
||||
*/
|
||||
static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
|
||||
enum meson_reg_type reg_type,
|
||||
unsigned int *reg, unsigned int *bit)
|
||||
{
|
||||
struct meson_reg_desc *desc = &bank->regs[reg_type];
|
||||
|
||||
*reg = desc->reg * 4;
|
||||
*bit = desc->bit + pin - bank->first;
|
||||
}
|
||||
|
||||
static int meson_get_groups_count(struct pinctrl_dev *pcdev)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
|
||||
return pc->data->num_groups;
|
||||
}
|
||||
|
||||
static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
|
||||
return pc->data->groups[selector].name;
|
||||
}
|
||||
|
||||
static int meson_get_group_pins(struct pinctrl_dev *pcdev,
|
||||
unsigned int selector, const unsigned int **pins,
|
||||
unsigned int *num_pins)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
|
||||
*pins = pc->data->groups[selector].pins;
|
||||
*num_pins = pc->data->groups[selector].num_pins;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
|
||||
unsigned int offset)
|
||||
{
|
||||
seq_printf(s, " %s", dev_name(pcdev->dev));
|
||||
}
|
||||
|
||||
static const struct pinctrl_ops meson_pctrl_ops = {
|
||||
.get_groups_count = meson_get_groups_count,
|
||||
.get_group_name = meson_get_group_name,
|
||||
.get_group_pins = meson_get_group_pins,
|
||||
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
|
||||
.dt_free_map = pinctrl_utils_free_map,
|
||||
.pin_dbg_show = meson_pin_dbg_show,
|
||||
};
|
||||
|
||||
/**
|
||||
* meson_pmx_disable_other_groups() - disable other groups using a given pin
|
||||
*
|
||||
* @pc: meson pin controller device
|
||||
* @pin: number of the pin
|
||||
* @sel_group: index of the selected group, or -1 if none
|
||||
*
|
||||
* The function disables all pinmux groups using a pin except the
|
||||
* selected one. If @sel_group is -1 all groups are disabled, leaving
|
||||
* the pin in GPIO mode.
|
||||
*/
|
||||
static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
|
||||
unsigned int pin, int sel_group)
|
||||
{
|
||||
struct meson_pmx_group *group;
|
||||
struct meson_domain *domain;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < pc->data->num_groups; i++) {
|
||||
group = &pc->data->groups[i];
|
||||
if (group->is_gpio || i == sel_group)
|
||||
continue;
|
||||
|
||||
for (j = 0; j < group->num_pins; j++) {
|
||||
if (group->pins[j] == pin) {
|
||||
/* We have found a group using the pin */
|
||||
domain = pc->domain;
|
||||
regmap_update_bits(domain->reg_mux,
|
||||
group->reg * 4,
|
||||
BIT(group->bit), 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int meson_pmx_set_mux(struct pinctrl_dev *pcdev,
|
||||
unsigned int func_num, unsigned int group_num)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
struct meson_pmx_func *func = &pc->data->funcs[func_num];
|
||||
struct meson_pmx_group *group = &pc->data->groups[group_num];
|
||||
struct meson_domain *domain = pc->domain;
|
||||
int i, ret = 0;
|
||||
|
||||
dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
|
||||
group->name);
|
||||
|
||||
/*
|
||||
* Disable groups using the same pin.
|
||||
* The selected group is not disabled to avoid glitches.
|
||||
*/
|
||||
for (i = 0; i < group->num_pins; i++)
|
||||
meson_pmx_disable_other_groups(pc, group->pins[i], group_num);
|
||||
|
||||
/* Function 0 (GPIO) doesn't need any additional setting */
|
||||
if (func_num && (group->bit != 0xff))
|
||||
ret = regmap_update_bits(domain->reg_mux, group->reg * 4,
|
||||
BIT(group->bit), BIT(group->bit));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned int offset)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
|
||||
meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
|
||||
return pc->data->num_funcs;
|
||||
}
|
||||
|
||||
static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
|
||||
return pc->data->funcs[selector].name;
|
||||
}
|
||||
|
||||
static int meson_pmx_get_groups(struct pinctrl_dev *pcdev,
|
||||
unsigned int selector, const char * const **groups,
|
||||
unsigned int * const num_groups)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
|
||||
*groups = pc->data->funcs[selector].groups;
|
||||
*num_groups = pc->data->funcs[selector].num_groups;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pinmux_ops meson_pmx_ops = {
|
||||
.set_mux = meson_pmx_set_mux,
|
||||
.get_functions_count = meson_pmx_get_funcs_count,
|
||||
.get_function_name = meson_pmx_get_func_name,
|
||||
.get_function_groups = meson_pmx_get_groups,
|
||||
.gpio_request_enable = meson_pmx_request_gpio,
|
||||
};
|
||||
|
||||
static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
|
||||
unsigned long *configs, unsigned int num_configs)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
struct meson_domain *domain;
|
||||
struct meson_bank *bank;
|
||||
enum pin_config_param param;
|
||||
unsigned int reg, bit;
|
||||
int i, ret;
|
||||
u16 arg;
|
||||
|
||||
ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < num_configs; i++) {
|
||||
param = pinconf_to_config_param(configs[i]);
|
||||
arg = pinconf_to_config_argument(configs[i]);
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
|
||||
ret = regmap_update_bits(domain->reg_pull, reg,
|
||||
BIT(bit), 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
|
||||
®, &bit);
|
||||
ret = regmap_update_bits(domain->reg_pullen, reg,
|
||||
BIT(bit), BIT(bit));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
|
||||
ret = regmap_update_bits(domain->reg_pull, reg,
|
||||
BIT(bit), BIT(bit));
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
|
||||
®, &bit);
|
||||
ret = regmap_update_bits(domain->reg_pullen, reg,
|
||||
BIT(bit), BIT(bit));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
|
||||
ret = regmap_update_bits(domain->reg_pull, reg,
|
||||
BIT(bit), 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
case PIN_CONFIG_INPUT_ENABLE:
|
||||
dev_dbg(pc->dev, "pin %u: enable input\n", pin);
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_DIR,
|
||||
®, &bit);
|
||||
ret = regmap_update_bits(domain->reg_gpio, reg,
|
||||
BIT(bit), BIT(bit));
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
|
||||
{
|
||||
struct meson_domain *domain;
|
||||
struct meson_bank *bank;
|
||||
unsigned int reg, bit, val;
|
||||
int ret, conf;
|
||||
|
||||
ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit);
|
||||
|
||||
ret = regmap_read(domain->reg_pullen, reg, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!(val & BIT(bit))) {
|
||||
conf = PIN_CONFIG_BIAS_DISABLE;
|
||||
} else {
|
||||
meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
|
||||
|
||||
ret = regmap_read(domain->reg_pull, reg, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (val & BIT(bit))
|
||||
conf = PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
conf = PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
return conf;
|
||||
}
|
||||
|
||||
static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
|
||||
unsigned long *config)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
enum pin_config_param param = pinconf_to_config_param(*config);
|
||||
u16 arg;
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
if (meson_pinconf_get_pull(pc, pin) == param)
|
||||
arg = 1;
|
||||
else
|
||||
return -EINVAL;
|
||||
break;
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
*config = pinconf_to_config_packed(param, arg);
|
||||
dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
|
||||
unsigned int num_group, unsigned long *configs,
|
||||
unsigned int num_configs)
|
||||
{
|
||||
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
||||
struct meson_pmx_group *group = &pc->data->groups[num_group];
|
||||
int i;
|
||||
|
||||
dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
|
||||
|
||||
for (i = 0; i < group->num_pins; i++) {
|
||||
meson_pinconf_set(pcdev, group->pins[i], configs,
|
||||
num_configs);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pinconf_ops meson_pinconf_ops = {
|
||||
.pin_config_get = meson_pinconf_get,
|
||||
.pin_config_set = meson_pinconf_set,
|
||||
.pin_config_group_set = meson_pinconf_group_set,
|
||||
.is_generic = true,
|
||||
};
|
||||
|
||||
static inline struct meson_domain *to_meson_domain(struct gpio_chip *chip)
|
||||
{
|
||||
return container_of(chip, struct meson_domain, chip);
|
||||
}
|
||||
|
||||
static int meson_gpio_request(struct gpio_chip *chip, unsigned int gpio)
|
||||
{
|
||||
return pinctrl_request_gpio(chip->base + gpio);
|
||||
}
|
||||
|
||||
static void meson_gpio_free(struct gpio_chip *chip, unsigned int gpio)
|
||||
{
|
||||
struct meson_domain *domain = to_meson_domain(chip);
|
||||
|
||||
pinctrl_free_gpio(domain->data->pin_base + gpio);
|
||||
}
|
||||
|
||||
static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
|
||||
{
|
||||
struct meson_domain *domain = to_meson_domain(chip);
|
||||
unsigned int reg, bit, pin;
|
||||
struct meson_bank *bank;
|
||||
int ret;
|
||||
|
||||
pin = domain->data->pin_base + gpio;
|
||||
ret = meson_get_bank(domain, pin, &bank);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit);
|
||||
|
||||
return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit));
|
||||
}
|
||||
|
||||
static int meson_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned int gpio, int value)
|
||||
{
|
||||
struct meson_domain *domain = to_meson_domain(chip);
|
||||
unsigned int reg, bit, pin;
|
||||
struct meson_bank *bank;
|
||||
int ret;
|
||||
|
||||
pin = domain->data->pin_base + gpio;
|
||||
ret = meson_get_bank(domain, pin, &bank);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit);
|
||||
ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit);
|
||||
return regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
|
||||
value ? BIT(bit) : 0);
|
||||
}
|
||||
|
||||
static void meson_gpio_set(struct gpio_chip *chip, unsigned int gpio,
|
||||
int value)
|
||||
{
|
||||
struct meson_domain *domain = to_meson_domain(chip);
|
||||
unsigned int reg, bit, pin;
|
||||
struct meson_bank *bank;
|
||||
int ret;
|
||||
|
||||
pin = domain->data->pin_base + gpio;
|
||||
ret = meson_get_bank(domain, pin, &bank);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit);
|
||||
regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
|
||||
value ? BIT(bit) : 0);
|
||||
}
|
||||
|
||||
static int meson_gpio_get(struct gpio_chip *chip, unsigned int gpio)
|
||||
{
|
||||
struct meson_domain *domain = to_meson_domain(chip);
|
||||
unsigned int reg, bit, val, pin;
|
||||
struct meson_bank *bank;
|
||||
int ret;
|
||||
|
||||
pin = domain->data->pin_base + gpio;
|
||||
ret = meson_get_bank(domain, pin, &bank);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit);
|
||||
regmap_read(domain->reg_gpio, reg, &val);
|
||||
|
||||
return !!(val & BIT(bit));
|
||||
}
|
||||
|
||||
static const struct of_device_id meson_pinctrl_dt_match[] = {
|
||||
{
|
||||
.compatible = "amlogic,meson-gxl-periphs-pinctrl",
|
||||
.data = &meson_gxl_periphs_pinctrl_data,
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-gxl-aobus-pinctrl",
|
||||
.data = &meson_gxl_aobus_pinctrl_data,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
|
||||
|
||||
static int meson_gpiolib_register(struct meson_pinctrl *pc)
|
||||
{
|
||||
struct meson_domain *domain;
|
||||
int ret;
|
||||
|
||||
domain = pc->domain;
|
||||
|
||||
domain->chip.label = domain->data->name;
|
||||
/* domain->chip.dev = pc->dev; */
|
||||
domain->chip.request = meson_gpio_request;
|
||||
domain->chip.free = meson_gpio_free;
|
||||
domain->chip.direction_input = meson_gpio_direction_input;
|
||||
domain->chip.direction_output = meson_gpio_direction_output;
|
||||
domain->chip.get = meson_gpio_get;
|
||||
domain->chip.set = meson_gpio_set;
|
||||
domain->chip.base = domain->data->pin_base;
|
||||
domain->chip.ngpio = domain->data->num_pins;
|
||||
domain->chip.can_sleep = false;
|
||||
domain->chip.of_node = domain->of_node;
|
||||
domain->chip.of_gpio_n_cells = 2;
|
||||
|
||||
ret = gpiochip_add(&domain->chip);
|
||||
if (ret) {
|
||||
dev_err(pc->dev, "can't add gpio chip %s\n",
|
||||
domain->data->name);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
|
||||
0, domain->data->pin_base,
|
||||
domain->chip.ngpio);
|
||||
if (ret) {
|
||||
dev_err(pc->dev, "can't add pin range\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return 0;
|
||||
fail:
|
||||
gpiochip_remove(&pc->domain->chip);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct regmap_config meson_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
};
|
||||
|
||||
static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
|
||||
struct device_node *node, char *name)
|
||||
{
|
||||
struct resource res;
|
||||
void __iomem *base;
|
||||
int i;
|
||||
|
||||
i = of_property_match_string(node, "reg-names", name);
|
||||
if (of_address_to_resource(node, i, &res))
|
||||
return ERR_PTR(-ENOENT);
|
||||
|
||||
base = devm_ioremap_resource(pc->dev, &res);
|
||||
if (IS_ERR(base))
|
||||
return ERR_CAST(base);
|
||||
|
||||
meson_regmap_config.max_register = resource_size(&res) - 4;
|
||||
meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
|
||||
"%s-%s", node->name,
|
||||
name);
|
||||
if (!meson_regmap_config.name)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
|
||||
}
|
||||
|
||||
static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct meson_domain *domain;
|
||||
int num_domains = 0;
|
||||
|
||||
for_each_child_of_node(node, np) {
|
||||
if (!of_find_property(np, "gpio-controller", NULL))
|
||||
continue;
|
||||
num_domains++;
|
||||
}
|
||||
|
||||
if (num_domains != 1) {
|
||||
dev_err(pc->dev, "wrong number of subnodes\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pc->domain = devm_kzalloc(pc->dev, sizeof(struct meson_domain),
|
||||
GFP_KERNEL);
|
||||
if (!pc->domain)
|
||||
return -ENOMEM;
|
||||
|
||||
domain = pc->domain;
|
||||
domain->data = pc->data->domain_data;
|
||||
|
||||
for_each_child_of_node(node, np) {
|
||||
if (!of_find_property(np, "gpio-controller", NULL))
|
||||
continue;
|
||||
|
||||
domain->of_node = np;
|
||||
|
||||
domain->reg_mux = meson_map_resource(pc, np, "mux");
|
||||
if (IS_ERR(domain->reg_mux)) {
|
||||
dev_err(pc->dev, "mux registers not found\n");
|
||||
return PTR_ERR(domain->reg_mux);
|
||||
}
|
||||
|
||||
domain->reg_pull = meson_map_resource(pc, np, "pull");
|
||||
if (IS_ERR(domain->reg_pull)) {
|
||||
dev_err(pc->dev, "pull registers not found\n");
|
||||
return PTR_ERR(domain->reg_pull);
|
||||
}
|
||||
|
||||
domain->reg_pullen = meson_map_resource(pc, np, "pull-enable");
|
||||
/* Use pull region if pull-enable one is not present */
|
||||
if (IS_ERR(domain->reg_pullen))
|
||||
domain->reg_pullen = domain->reg_pull;
|
||||
|
||||
domain->reg_gpio = meson_map_resource(pc, np, "gpio");
|
||||
if (IS_ERR(domain->reg_gpio)) {
|
||||
dev_err(pc->dev, "gpio registers not found\n");
|
||||
return PTR_ERR(domain->reg_gpio);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int meson_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct meson_pinctrl *pc;
|
||||
int ret;
|
||||
|
||||
pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
|
||||
if (!pc)
|
||||
return -ENOMEM;
|
||||
|
||||
pc->dev = dev;
|
||||
match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node);
|
||||
pc->data = (struct meson_pinctrl_data *) match->data;
|
||||
|
||||
ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pc->desc.name = "pinctrl-meson";
|
||||
pc->desc.owner = THIS_MODULE;
|
||||
pc->desc.pctlops = &meson_pctrl_ops;
|
||||
pc->desc.pmxops = &meson_pmx_ops;
|
||||
pc->desc.confops = &meson_pinconf_ops;
|
||||
pc->desc.pins = pc->data->pins;
|
||||
pc->desc.npins = pc->data->num_pins;
|
||||
|
||||
pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc);
|
||||
if (IS_ERR(pc->pcdev)) {
|
||||
dev_err(pc->dev, "can't register pinctrl device");
|
||||
return PTR_ERR(pc->pcdev);
|
||||
}
|
||||
|
||||
ret = meson_gpiolib_register(pc);
|
||||
if (ret) {
|
||||
pinctrl_unregister(pc->pcdev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver meson_pinctrl_driver = {
|
||||
.probe = meson_pinctrl_probe,
|
||||
.driver = {
|
||||
.name = "meson-pinctrl",
|
||||
.of_match_table = meson_pinctrl_dt_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init gxl_pmx_init(void)
|
||||
{
|
||||
return platform_driver_register(&meson_pinctrl_driver);
|
||||
}
|
||||
|
||||
static void __exit gxl_pmx_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&meson_pinctrl_driver);
|
||||
}
|
||||
|
||||
arch_initcall(gxl_pmx_init);
|
||||
module_exit(gxl_pmx_exit);
|
||||
MODULE_DESCRIPTION("gxl pin control driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
207
drivers/amlogic/pinctrl/pinctrl-meson.h
Normal file
207
drivers/amlogic/pinctrl/pinctrl-meson.h
Normal file
@@ -0,0 +1,207 @@
|
||||
/*
|
||||
* drivers/amlogic/pinctrl/pinctrl-meson.h
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
/**
|
||||
* struct meson_pmx_group - a pinmux group
|
||||
*
|
||||
* @name: group name
|
||||
* @pins: pins in the group
|
||||
* @num_pins: number of pins in the group
|
||||
* @is_gpio: whether the group is a single GPIO group
|
||||
* @reg: register offset for the group in the domain mux registers
|
||||
* @bit bit index enabling the group
|
||||
* @domain: index of the domain this group belongs to
|
||||
*/
|
||||
struct meson_pmx_group {
|
||||
const char *name;
|
||||
const unsigned int *pins;
|
||||
unsigned int num_pins;
|
||||
bool is_gpio;
|
||||
unsigned int reg;
|
||||
unsigned int bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct meson_pmx_func - a pinmux function
|
||||
*
|
||||
* @name: function name
|
||||
* @groups: groups in the function
|
||||
* @num_groups: number of groups in the function
|
||||
*/
|
||||
struct meson_pmx_func {
|
||||
const char *name;
|
||||
const char * const *groups;
|
||||
unsigned int num_groups;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct meson_reg_desc - a register descriptor
|
||||
*
|
||||
* @reg: register offset in the regmap
|
||||
* @bit: bit index in register
|
||||
*
|
||||
* The structure describes the information needed to control pull,
|
||||
* pull-enable, direction, etc. for a single pin
|
||||
*/
|
||||
struct meson_reg_desc {
|
||||
unsigned int reg;
|
||||
unsigned int bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum meson_reg_type - type of registers encoded in @meson_reg_desc
|
||||
*/
|
||||
enum meson_reg_type {
|
||||
REG_PULLEN,
|
||||
REG_PULL,
|
||||
REG_DIR,
|
||||
REG_OUT,
|
||||
REG_IN,
|
||||
NUM_REG,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct meson bank
|
||||
*
|
||||
* @name: bank name
|
||||
* @first: first pin of the bank
|
||||
* @last: last pin of the bank
|
||||
* @regs: array of register descriptors
|
||||
*
|
||||
* A bank represents a set of pins controlled by a contiguous set of
|
||||
* bits in the domain registers. The structure specifies which bits in
|
||||
* the regmap control the different functionalities. Each member of
|
||||
* the @regs array refers to the first pin of the bank.
|
||||
*/
|
||||
struct meson_bank {
|
||||
const char *name;
|
||||
unsigned int first;
|
||||
unsigned int last;
|
||||
struct meson_reg_desc regs[NUM_REG];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct meson_domain_data - domain platform data
|
||||
*
|
||||
* @name: name of the domain
|
||||
* @banks: set of banks belonging to the domain
|
||||
* @num_banks: number of banks in the domain
|
||||
*/
|
||||
struct meson_domain_data {
|
||||
const char *name;
|
||||
struct meson_bank *banks;
|
||||
unsigned int num_banks;
|
||||
unsigned int pin_base;
|
||||
unsigned int num_pins;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct meson_domain
|
||||
*
|
||||
* @reg_mux: registers for mux settings
|
||||
* @reg_pullen: registers for pull-enable settings
|
||||
* @reg_pull: registers for pull settings
|
||||
* @reg_gpio: registers for gpio settings
|
||||
* @chip: gpio chip associated with the domain
|
||||
* @data; platform data for the domain
|
||||
* @node: device tree node for the domain
|
||||
*
|
||||
* A domain represents a set of banks controlled by the same set of
|
||||
* registers.
|
||||
*/
|
||||
struct meson_domain {
|
||||
struct regmap *reg_mux;
|
||||
struct regmap *reg_pullen;
|
||||
struct regmap *reg_pull;
|
||||
struct regmap *reg_gpio;
|
||||
|
||||
struct gpio_chip chip;
|
||||
struct meson_domain_data *data;
|
||||
struct device_node *of_node;
|
||||
};
|
||||
|
||||
struct meson_pinctrl_data {
|
||||
const struct pinctrl_pin_desc *pins;
|
||||
struct meson_pmx_group *groups;
|
||||
struct meson_pmx_func *funcs;
|
||||
struct meson_domain_data *domain_data;
|
||||
unsigned int num_pins;
|
||||
unsigned int num_groups;
|
||||
unsigned int num_funcs;
|
||||
};
|
||||
|
||||
struct meson_pinctrl {
|
||||
struct device *dev;
|
||||
struct pinctrl_dev *pcdev;
|
||||
struct pinctrl_desc desc;
|
||||
struct meson_pinctrl_data *data;
|
||||
struct meson_domain *domain;
|
||||
};
|
||||
|
||||
#define PIN(x, b) (b + x)
|
||||
|
||||
#define GROUP(grp, r, b) \
|
||||
{ \
|
||||
.name = #grp, \
|
||||
.pins = grp ## _pins, \
|
||||
.num_pins = ARRAY_SIZE(grp ## _pins), \
|
||||
.reg = r, \
|
||||
.bit = b, \
|
||||
}
|
||||
|
||||
#define GPIO_GROUP(gpio, b) \
|
||||
{ \
|
||||
.name = #gpio, \
|
||||
.pins = (const unsigned int[]){ PIN(gpio, b) }, \
|
||||
.num_pins = 1, \
|
||||
.is_gpio = true, \
|
||||
}
|
||||
|
||||
#define FUNCTION(fn) \
|
||||
{ \
|
||||
.name = #fn, \
|
||||
.groups = fn ## _groups, \
|
||||
.num_groups = ARRAY_SIZE(fn ## _groups), \
|
||||
}
|
||||
|
||||
#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
|
||||
{ \
|
||||
.name = n, \
|
||||
.first = f, \
|
||||
.last = l, \
|
||||
.regs = { \
|
||||
[REG_PULLEN] = { per, peb }, \
|
||||
[REG_PULL] = { pr, pb }, \
|
||||
[REG_DIR] = { dr, db }, \
|
||||
[REG_OUT] = { or, ob }, \
|
||||
[REG_IN] = { ir, ib }, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
|
||||
|
||||
extern struct meson_pinctrl_data meson8_cbus_pinctrl_data;
|
||||
extern struct meson_pinctrl_data meson8_aobus_pinctrl_data;
|
||||
extern struct meson_pinctrl_data meson8b_cbus_pinctrl_data;
|
||||
extern struct meson_pinctrl_data meson8b_aobus_pinctrl_data;
|
||||
extern struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data;
|
||||
extern struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data;
|
||||
987
drivers/amlogic/pinctrl/pinctrl_gxl.c
Normal file
987
drivers/amlogic/pinctrl/pinctrl_gxl.c
Normal file
@@ -0,0 +1,987 @@
|
||||
/*
|
||||
* drivers/amlogic/pinctrl/pinctrl_gxl.c
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "pinctrl-meson.h"
|
||||
#include <dt-bindings/gpio/gxl.h>
|
||||
|
||||
#define EE_OFF 10
|
||||
|
||||
static const struct pinctrl_pin_desc meson_gxl_periphs_pins[] = {
|
||||
MESON_PIN(GPIOZ_0, EE_OFF),
|
||||
MESON_PIN(GPIOZ_1, EE_OFF),
|
||||
MESON_PIN(GPIOZ_2, EE_OFF),
|
||||
MESON_PIN(GPIOZ_3, EE_OFF),
|
||||
MESON_PIN(GPIOZ_4, EE_OFF),
|
||||
MESON_PIN(GPIOZ_5, EE_OFF),
|
||||
MESON_PIN(GPIOZ_6, EE_OFF),
|
||||
MESON_PIN(GPIOZ_7, EE_OFF),
|
||||
MESON_PIN(GPIOZ_8, EE_OFF),
|
||||
MESON_PIN(GPIOZ_9, EE_OFF),
|
||||
MESON_PIN(GPIOZ_10, EE_OFF),
|
||||
MESON_PIN(GPIOZ_11, EE_OFF),
|
||||
MESON_PIN(GPIOZ_12, EE_OFF),
|
||||
MESON_PIN(GPIOZ_13, EE_OFF),
|
||||
MESON_PIN(GPIOZ_14, EE_OFF),
|
||||
MESON_PIN(GPIOZ_15, EE_OFF),
|
||||
MESON_PIN(GPIOH_0, EE_OFF),
|
||||
MESON_PIN(GPIOH_1, EE_OFF),
|
||||
MESON_PIN(GPIOH_2, EE_OFF),
|
||||
MESON_PIN(GPIOH_3, EE_OFF),
|
||||
MESON_PIN(GPIOH_4, EE_OFF),
|
||||
MESON_PIN(GPIOH_5, EE_OFF),
|
||||
MESON_PIN(GPIOH_6, EE_OFF),
|
||||
MESON_PIN(GPIOH_7, EE_OFF),
|
||||
MESON_PIN(GPIOH_8, EE_OFF),
|
||||
MESON_PIN(GPIOH_9, EE_OFF),
|
||||
MESON_PIN(BOOT_0, EE_OFF),
|
||||
MESON_PIN(BOOT_1, EE_OFF),
|
||||
MESON_PIN(BOOT_2, EE_OFF),
|
||||
MESON_PIN(BOOT_3, EE_OFF),
|
||||
MESON_PIN(BOOT_4, EE_OFF),
|
||||
MESON_PIN(BOOT_5, EE_OFF),
|
||||
MESON_PIN(BOOT_6, EE_OFF),
|
||||
MESON_PIN(BOOT_7, EE_OFF),
|
||||
MESON_PIN(BOOT_8, EE_OFF),
|
||||
MESON_PIN(BOOT_9, EE_OFF),
|
||||
MESON_PIN(BOOT_10, EE_OFF),
|
||||
MESON_PIN(BOOT_11, EE_OFF),
|
||||
MESON_PIN(BOOT_12, EE_OFF),
|
||||
MESON_PIN(BOOT_13, EE_OFF),
|
||||
MESON_PIN(BOOT_14, EE_OFF),
|
||||
MESON_PIN(BOOT_15, EE_OFF),
|
||||
MESON_PIN(CARD_0, EE_OFF),
|
||||
MESON_PIN(CARD_1, EE_OFF),
|
||||
MESON_PIN(CARD_2, EE_OFF),
|
||||
MESON_PIN(CARD_3, EE_OFF),
|
||||
MESON_PIN(CARD_4, EE_OFF),
|
||||
MESON_PIN(CARD_5, EE_OFF),
|
||||
MESON_PIN(CARD_6, EE_OFF),
|
||||
MESON_PIN(GPIODV_0, EE_OFF),
|
||||
MESON_PIN(GPIODV_1, EE_OFF),
|
||||
MESON_PIN(GPIODV_2, EE_OFF),
|
||||
MESON_PIN(GPIODV_3, EE_OFF),
|
||||
MESON_PIN(GPIODV_4, EE_OFF),
|
||||
MESON_PIN(GPIODV_5, EE_OFF),
|
||||
MESON_PIN(GPIODV_6, EE_OFF),
|
||||
MESON_PIN(GPIODV_7, EE_OFF),
|
||||
MESON_PIN(GPIODV_8, EE_OFF),
|
||||
MESON_PIN(GPIODV_9, EE_OFF),
|
||||
MESON_PIN(GPIODV_10, EE_OFF),
|
||||
MESON_PIN(GPIODV_11, EE_OFF),
|
||||
MESON_PIN(GPIODV_12, EE_OFF),
|
||||
MESON_PIN(GPIODV_13, EE_OFF),
|
||||
MESON_PIN(GPIODV_14, EE_OFF),
|
||||
MESON_PIN(GPIODV_15, EE_OFF),
|
||||
MESON_PIN(GPIODV_16, EE_OFF),
|
||||
MESON_PIN(GPIODV_17, EE_OFF),
|
||||
MESON_PIN(GPIODV_18, EE_OFF),
|
||||
MESON_PIN(GPIODV_19, EE_OFF),
|
||||
MESON_PIN(GPIODV_20, EE_OFF),
|
||||
MESON_PIN(GPIODV_21, EE_OFF),
|
||||
MESON_PIN(GPIODV_22, EE_OFF),
|
||||
MESON_PIN(GPIODV_23, EE_OFF),
|
||||
MESON_PIN(GPIODV_24, EE_OFF),
|
||||
MESON_PIN(GPIODV_25, EE_OFF),
|
||||
MESON_PIN(GPIODV_26, EE_OFF),
|
||||
MESON_PIN(GPIODV_27, EE_OFF),
|
||||
MESON_PIN(GPIODV_28, EE_OFF),
|
||||
MESON_PIN(GPIODV_29, EE_OFF),
|
||||
MESON_PIN(GPIOX_0, EE_OFF),
|
||||
MESON_PIN(GPIOX_1, EE_OFF),
|
||||
MESON_PIN(GPIOX_2, EE_OFF),
|
||||
MESON_PIN(GPIOX_3, EE_OFF),
|
||||
MESON_PIN(GPIOX_4, EE_OFF),
|
||||
MESON_PIN(GPIOX_5, EE_OFF),
|
||||
MESON_PIN(GPIOX_6, EE_OFF),
|
||||
MESON_PIN(GPIOX_7, EE_OFF),
|
||||
MESON_PIN(GPIOX_8, EE_OFF),
|
||||
MESON_PIN(GPIOX_9, EE_OFF),
|
||||
MESON_PIN(GPIOX_10, EE_OFF),
|
||||
MESON_PIN(GPIOX_11, EE_OFF),
|
||||
MESON_PIN(GPIOX_12, EE_OFF),
|
||||
MESON_PIN(GPIOX_13, EE_OFF),
|
||||
MESON_PIN(GPIOX_14, EE_OFF),
|
||||
MESON_PIN(GPIOX_15, EE_OFF),
|
||||
MESON_PIN(GPIOX_16, EE_OFF),
|
||||
MESON_PIN(GPIOX_17, EE_OFF),
|
||||
MESON_PIN(GPIOX_18, EE_OFF),
|
||||
MESON_PIN(GPIOCLK_0, EE_OFF),
|
||||
MESON_PIN(GPIOCLK_1, EE_OFF),
|
||||
|
||||
MESON_PIN(GPIO_TEST_N, EE_OFF),
|
||||
};
|
||||
|
||||
static const unsigned int emmc_nand_d07_pins[] = {
|
||||
PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
|
||||
PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
|
||||
PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
|
||||
};
|
||||
|
||||
static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) };
|
||||
static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) };
|
||||
static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) };
|
||||
static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) };
|
||||
static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) };
|
||||
static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) };
|
||||
static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) };
|
||||
static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) };
|
||||
|
||||
static const unsigned int tst_clk_0_pins[] = { PIN(BOOT_3, EE_OFF) };
|
||||
|
||||
static const unsigned int tst_clk_6_pins[] = { PIN(BOOT_9, EE_OFF) };
|
||||
|
||||
|
||||
static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
|
||||
static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
|
||||
static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
|
||||
|
||||
/*card0*/
|
||||
static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
|
||||
/*card1*/
|
||||
static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
|
||||
/*card2*/
|
||||
static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
|
||||
/*card3*/
|
||||
static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
|
||||
|
||||
static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
|
||||
static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
|
||||
|
||||
static const unsigned int tst_clk_9_pins[] = { PIN(CARD_4, EE_OFF) };
|
||||
|
||||
static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) };
|
||||
static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) };
|
||||
static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) };
|
||||
static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) };
|
||||
static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_4, EE_OFF) };
|
||||
static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_5, EE_OFF) };
|
||||
|
||||
|
||||
static const unsigned int pwm_a_pins[] = { PIN(GPIOX_6, EE_OFF) };
|
||||
|
||||
static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) };
|
||||
static const unsigned int pwm_f_pins[] = { PIN(GPIOX_7, EE_OFF) };
|
||||
|
||||
static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) };
|
||||
static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) };
|
||||
static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) };
|
||||
static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) };
|
||||
|
||||
static const unsigned int pwm_e_pins[] = { PIN(GPIOX_16, EE_OFF) };
|
||||
|
||||
|
||||
/*bank H*/
|
||||
static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) };
|
||||
static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) };
|
||||
static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) };
|
||||
|
||||
/*H4*/
|
||||
static const unsigned int spdif_out_pins[] = { PIN(GPIOH_4, EE_OFF),
|
||||
/*PIN(GPIOAO_6, 0) */ };
|
||||
|
||||
|
||||
/*H6*/
|
||||
static const unsigned int jtag_clk_0_pins[] = { PIN(GPIOH_6, EE_OFF) };
|
||||
static const unsigned int jtag_clk_1_pins[] = { PIN(CARD_2, EE_OFF) };
|
||||
|
||||
static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOH_6, EE_OFF) };
|
||||
static const unsigned int tsin_clk_b_h6_pins[] = { PIN(GPIOH_6, EE_OFF) };
|
||||
|
||||
/*H7*/
|
||||
static const unsigned int jtag_tms_0_pins[] = { PIN(GPIOH_7, EE_OFF) };
|
||||
static const unsigned int jtag_tms_1_pins[] = { PIN(CARD_3, EE_OFF) };
|
||||
|
||||
static const unsigned int i2s_ao_clk_out_pins[] = { PIN(GPIOH_7, EE_OFF) };
|
||||
static const unsigned int i2s_ao_clk_in_h7_pins[] = { PIN(GPIOH_7, EE_OFF) };
|
||||
static const unsigned int tsin_d0_b_h7_pins[] = { PIN(GPIOH_7, EE_OFF) };
|
||||
|
||||
/*H8*/
|
||||
static const unsigned int jtag_tdi_0_pins[] = { PIN(GPIOH_8, EE_OFF) };
|
||||
static const unsigned int jtag_tdi_1_pins[] = { PIN(CARD_0, EE_OFF) };
|
||||
|
||||
|
||||
static const unsigned int i2s_lr_clk_out_pins[] = { PIN(GPIOH_8, EE_OFF) };
|
||||
static const unsigned int i2s_lr_clk_in_h8_pins[] = { PIN(GPIOH_8, EE_OFF) };
|
||||
static const unsigned int tsin_sop_b_h8_pins[] = { PIN(GPIOH_8, EE_OFF) };
|
||||
|
||||
|
||||
/*H8*/
|
||||
static const unsigned int jtag_tdo_0_pins[] = { PIN(GPIOH_9, EE_OFF) };
|
||||
static const unsigned int jtag_tdo_1_pins[] = { PIN(CARD_1, EE_OFF) };
|
||||
|
||||
static const unsigned int i2sout_ch01_pins[] = { PIN(GPIOH_9, EE_OFF) };
|
||||
static const unsigned int tsin_d_valid_b_h9_pins[] = { PIN(GPIOH_9, EE_OFF) };
|
||||
|
||||
|
||||
|
||||
static const unsigned int lcd_vs_pins[] = { PIN(GPIODV_24, EE_OFF) };
|
||||
static const unsigned int dmic_in_pins[] = { PIN(GPIODV_24, EE_OFF) };
|
||||
static const unsigned int tcon_stv1_pins[] = { PIN(GPIODV_24, EE_OFF) };
|
||||
|
||||
static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) };
|
||||
static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) };
|
||||
static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) };
|
||||
static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) };
|
||||
|
||||
static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) };
|
||||
static const unsigned int i2c_scl_a_pins[] = { PIN(GPIODV_25, EE_OFF) };
|
||||
|
||||
static const unsigned int i2c_sda_b_pins[] = { PIN(GPIODV_26, EE_OFF) };
|
||||
static const unsigned int i2c_scl_b_pins[] = { PIN(GPIODV_27, EE_OFF) };
|
||||
|
||||
|
||||
static const unsigned int i2c_sda_c_pins[] = { PIN(GPIODV_28, EE_OFF) };
|
||||
static const unsigned int i2c_scl_c_pins[] = { PIN(GPIODV_29, EE_OFF) };
|
||||
|
||||
static const unsigned int i2c_sda_c_1_pins[] = { PIN(GPIODV_18, EE_OFF) };
|
||||
static const unsigned int i2c_scl_c_1_pins[] = { PIN(GPIODV_19, EE_OFF) };
|
||||
|
||||
|
||||
static const unsigned int uart_tx_c_pins[] = { PIN(GPIOX_8, EE_OFF) };
|
||||
static const unsigned int uart_rx_c_pins[] = { PIN(GPIOX_9, EE_OFF) };
|
||||
static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_10, EE_OFF) };
|
||||
static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_11, EE_OFF) };
|
||||
|
||||
static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_8, EE_OFF) };
|
||||
static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_9, EE_OFF) };
|
||||
static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_10, EE_OFF) };
|
||||
static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_11, EE_OFF) };
|
||||
|
||||
static const unsigned int i2c_sda_d_pins[] = { PIN(GPIOX_10, EE_OFF) };
|
||||
static const unsigned int i2c_scl_d_pins[] = { PIN(GPIOX_11, EE_OFF) };
|
||||
|
||||
/*z0*/
|
||||
static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) };
|
||||
static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOZ_0, EE_OFF) };
|
||||
static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOZ_0, EE_OFF) };
|
||||
static const unsigned int dvp_vs_pins[] = { PIN(GPIOZ_0, EE_OFF) };
|
||||
|
||||
/*z1*/
|
||||
static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) };
|
||||
static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOZ_1, EE_OFF) };
|
||||
static const unsigned int tsin_sop_b_pins[] = { PIN(GPIOZ_1, EE_OFF) };
|
||||
static const unsigned int dvp_hs_pins[] = { PIN(GPIOZ_1, EE_OFF) };
|
||||
/*z2*/
|
||||
static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) };
|
||||
static const unsigned int i2sin_ch23_pins[] = { PIN(GPIOZ_2, EE_OFF) };
|
||||
static const unsigned int tsin_d0_b_pins[] = { PIN(GPIOZ_2, EE_OFF) };
|
||||
/*z3*/
|
||||
static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) };
|
||||
static const unsigned int i2sin_ch45_pins[] = { PIN(GPIOZ_3, EE_OFF) };
|
||||
static const unsigned int tsin_clk_b_pins[] = { PIN(GPIOZ_3, EE_OFF) };
|
||||
static const unsigned int dvp_clk_pins[] = { PIN(GPIOZ_3, EE_OFF) };
|
||||
/*z4*/
|
||||
static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) };
|
||||
static const unsigned int i2cin_ch67_pins[] = { PIN(GPIOZ_4, EE_OFF) };
|
||||
static const unsigned int tsin_fail_b_pins[] = { PIN(GPIOZ_4, EE_OFF) };
|
||||
static const unsigned int dvp_d2_pins[] = { PIN(GPIOZ_4, EE_OFF) };
|
||||
/*z5*/
|
||||
static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) };
|
||||
static const unsigned int i2sout_ch23_z5_pins[] = { PIN(GPIOZ_5, EE_OFF) };
|
||||
static const unsigned int dvp_d3_pins[] = { PIN(GPIOZ_5, EE_OFF) };
|
||||
/*z6*/
|
||||
static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) };
|
||||
static const unsigned int iso7816_clk_pins[] = { PIN(GPIOZ_6, EE_OFF) };
|
||||
static const unsigned int i2sout_ch45_pins[] = { PIN(GPIOZ_6, EE_OFF) };
|
||||
static const unsigned int dvp_d4_pins[] = { PIN(GPIOZ_6, EE_OFF) };
|
||||
|
||||
|
||||
static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) };
|
||||
static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) };
|
||||
static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) };
|
||||
static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) };
|
||||
static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) };
|
||||
static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) };
|
||||
static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) };
|
||||
|
||||
static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOZ_11, EE_OFF) };
|
||||
static const unsigned int spi_miso_0_pins[] = { PIN(GPIOZ_12, EE_OFF) };
|
||||
static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOZ_13, EE_OFF) };
|
||||
|
||||
static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOX_11, EE_OFF) };
|
||||
static const unsigned int spi_miso_1_pins[] = { PIN(GPIOX_9, EE_OFF) };
|
||||
static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOX_8, EE_OFF) };
|
||||
|
||||
|
||||
static const unsigned int spdif_in_pins[] = { PIN(GPIOZ_14, EE_OFF) };
|
||||
static const unsigned int eth_link_led_pins[] = { PIN(GPIOZ_14, EE_OFF) };
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*ao_0*/
|
||||
static const unsigned int uart_tx_ao_a_0_pins[] = { PIN(GPIOAO_0, 0) };
|
||||
static const unsigned int uart_rx_ao_a_0_pins[] = { PIN(GPIOAO_1, 0) };
|
||||
|
||||
static const unsigned int uart_tx_ao_a_1_pins[] = { PIN(CARD_4, 0) };
|
||||
static const unsigned int uart_rx_ao_a_1_pins[] = { PIN(CARD_5, 0) };
|
||||
|
||||
|
||||
static struct meson_pmx_group meson_gxl_periphs_groups[] = {
|
||||
GPIO_GROUP(GPIOZ_0, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_1, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_2, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_3, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_4, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_5, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_6, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_7, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_8, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_9, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_10, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_11, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_12, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_13, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_14, EE_OFF),
|
||||
GPIO_GROUP(GPIOZ_15, EE_OFF),
|
||||
GPIO_GROUP(GPIOH_0, EE_OFF),
|
||||
GPIO_GROUP(GPIOH_1, EE_OFF),
|
||||
GPIO_GROUP(GPIOH_2, EE_OFF),
|
||||
GPIO_GROUP(GPIOH_3, EE_OFF),
|
||||
GPIO_GROUP(GPIOH_4, EE_OFF),
|
||||
GPIO_GROUP(GPIOH_5, EE_OFF),
|
||||
GPIO_GROUP(GPIOH_6, EE_OFF),
|
||||
GPIO_GROUP(GPIOH_7, EE_OFF),
|
||||
GPIO_GROUP(GPIOH_8, EE_OFF),
|
||||
GPIO_GROUP(GPIOH_9, EE_OFF),
|
||||
GPIO_GROUP(BOOT_0, EE_OFF),
|
||||
GPIO_GROUP(BOOT_1, EE_OFF),
|
||||
GPIO_GROUP(BOOT_2, EE_OFF),
|
||||
GPIO_GROUP(BOOT_3, EE_OFF),
|
||||
GPIO_GROUP(BOOT_4, EE_OFF),
|
||||
GPIO_GROUP(BOOT_5, EE_OFF),
|
||||
GPIO_GROUP(BOOT_6, EE_OFF),
|
||||
GPIO_GROUP(BOOT_7, EE_OFF),
|
||||
GPIO_GROUP(BOOT_8, EE_OFF),
|
||||
GPIO_GROUP(BOOT_9, EE_OFF),
|
||||
GPIO_GROUP(BOOT_10, EE_OFF),
|
||||
GPIO_GROUP(BOOT_11, EE_OFF),
|
||||
GPIO_GROUP(BOOT_12, EE_OFF),
|
||||
GPIO_GROUP(BOOT_13, EE_OFF),
|
||||
GPIO_GROUP(BOOT_14, EE_OFF),
|
||||
GPIO_GROUP(BOOT_15, EE_OFF),
|
||||
GPIO_GROUP(CARD_0, EE_OFF),
|
||||
GPIO_GROUP(CARD_1, EE_OFF),
|
||||
GPIO_GROUP(CARD_2, EE_OFF),
|
||||
GPIO_GROUP(CARD_3, EE_OFF),
|
||||
GPIO_GROUP(CARD_4, EE_OFF),
|
||||
GPIO_GROUP(CARD_5, EE_OFF),
|
||||
GPIO_GROUP(CARD_6, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_0, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_1, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_2, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_3, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_4, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_5, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_6, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_7, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_8, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_9, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_10, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_11, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_12, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_13, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_14, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_15, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_16, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_17, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_18, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_19, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_20, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_21, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_22, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_23, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_24, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_25, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_26, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_27, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_28, EE_OFF),
|
||||
GPIO_GROUP(GPIODV_29, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_0, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_1, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_2, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_3, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_4, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_5, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_6, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_7, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_8, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_9, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_10, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_11, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_12, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_13, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_14, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_15, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_16, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_17, EE_OFF),
|
||||
GPIO_GROUP(GPIOX_18, EE_OFF),
|
||||
GPIO_GROUP(GPIOCLK_0, EE_OFF),
|
||||
GPIO_GROUP(GPIOCLK_1, EE_OFF),
|
||||
|
||||
GPIO_GROUP(GPIO_TEST_N, EE_OFF),
|
||||
|
||||
/* Bank X */
|
||||
GROUP(uart_tx_a, 5, 19),
|
||||
GROUP(uart_rx_a, 5, 18),
|
||||
GROUP(uart_cts_a, 5, 17),
|
||||
GROUP(uart_rts_a, 5, 16),
|
||||
|
||||
GROUP(uart_tx_c, 5, 13),
|
||||
GROUP(uart_rx_c, 5, 12),
|
||||
GROUP(uart_cts_c, 5, 11),
|
||||
GROUP(uart_rts_c, 5, 10),
|
||||
|
||||
|
||||
GROUP(pcm_out_a, 5, 23),
|
||||
GROUP(pcm_in_a, 5, 22),
|
||||
GROUP(pcm_fs_a, 5, 21),
|
||||
GROUP(pcm_clk_a, 5, 20),
|
||||
|
||||
|
||||
GROUP(pwm_e, 5, 15),
|
||||
|
||||
GROUP(sdio_d0, 5, 31), /*x0*/
|
||||
GROUP(sdio_d1, 5, 30), /*x1*/
|
||||
GROUP(sdio_d2, 5, 29), /*x2*/
|
||||
GROUP(sdio_d3, 5, 28), /*x3*/
|
||||
GROUP(sdio_clk, 5, 27), /*x4*/
|
||||
GROUP(sdio_cmd, 5, 26), /*x5*/
|
||||
|
||||
|
||||
GROUP(pwm_a, 5, 25), /*x6*/
|
||||
|
||||
GROUP(sdio_irq, 5, 24), /*x7*/
|
||||
GROUP(pwm_f, 5, 14), /*x7*/
|
||||
|
||||
GROUP(i2c_sda_d, 5, 5), /*x10*/
|
||||
GROUP(i2c_sda_d, 5, 4), /*x11*/
|
||||
|
||||
GROUP(spi_sclk_1, 5, 3),/*x8*/
|
||||
GROUP(spi_miso_1, 5, 2),/*x9*/
|
||||
GROUP(spi_mosi_1, 5, 0),/*x11*/
|
||||
|
||||
|
||||
|
||||
/* Bank H */
|
||||
GROUP(hdmi_hpd, 6, 31), /*H0*/
|
||||
GROUP(hdmi_sda, 6, 30), /*H1*/
|
||||
GROUP(hdmi_scl, 6, 29), /*H2*/
|
||||
|
||||
GROUP(spdif_out, 6, 28), /*H4*/
|
||||
|
||||
|
||||
GROUP(i2s_am_clk, 6, 26), /*H6*/
|
||||
GROUP(i2s_ao_clk_out, 6, 25), /*H7*/
|
||||
GROUP(i2s_lr_clk_out, 6, 24), /*H8*/
|
||||
GROUP(i2sout_ch01, 6, 23), /*H9*/
|
||||
|
||||
|
||||
GROUP(tsin_clk_b_h6, 6, 20), /*H6*/
|
||||
|
||||
GROUP(i2s_ao_clk_in_h7, 6, 22), /*H7*/
|
||||
GROUP(tsin_d0_b_h7, 6, 19), /*H7*/
|
||||
|
||||
GROUP(i2s_lr_clk_in_h8, 6, 21), /*H8*/
|
||||
GROUP(tsin_sop_b_h8, 6, 18), /*H8*/
|
||||
|
||||
GROUP(tsin_d_valid_b_h9, 6, 17), /*H9*/
|
||||
|
||||
|
||||
/* Bank Z */
|
||||
GROUP(eth_mdio, 4, 23), /*z0*/
|
||||
GROUP(eth_mdc, 4, 22), /*z1*/
|
||||
GROUP(eth_clk_rx_clk, 4, 21), /*z2*/
|
||||
GROUP(eth_rx_dv, 4, 20), /*z3*/
|
||||
GROUP(eth_rxd0, 4, 19), /*z4*/
|
||||
GROUP(eth_rxd1, 4, 18), /*z5*/
|
||||
GROUP(eth_rxd2, 4, 17), /*z6*/
|
||||
GROUP(eth_rxd3, 4, 16), /*z7*/
|
||||
GROUP(eth_rgmii_tx_clk, 4, 15), /*z8*/
|
||||
GROUP(eth_tx_en, 4, 14), /*z9*/
|
||||
GROUP(eth_txd0, 4, 13),/*z10*/
|
||||
GROUP(eth_txd1, 4, 12),/*z11*/
|
||||
GROUP(eth_txd2, 4, 11),/*z12*/
|
||||
GROUP(eth_txd3, 4, 10),/*z13*/
|
||||
|
||||
GROUP(i2s_ao_clk_in, 3, 31), /*z0*/
|
||||
GROUP(tsin_d_valid_b, 3, 19), /*z0*/
|
||||
GROUP(dvp_vs, 3, 14), /*z0*/
|
||||
|
||||
GROUP(i2s_lr_clk_in, 3, 30), /*z1*/
|
||||
GROUP(tsin_sop_b, 3, 18), /*z1*/
|
||||
GROUP(dvp_hs, 3, 13), /*z1*/
|
||||
|
||||
GROUP(i2sin_ch23, 3, 29), /*z2*/
|
||||
GROUP(tsin_d0_b, 3, 17), /*z2*/
|
||||
|
||||
|
||||
GROUP(i2sin_ch45, 3, 28), /*z3*/
|
||||
GROUP(tsin_clk_b, 3, 16), /*z3*/
|
||||
GROUP(dvp_clk, 3, 12), /*z3*/
|
||||
|
||||
GROUP(i2cin_ch67, 3, 27), /*z4*/
|
||||
GROUP(tsin_fail_b, 3, 15), /*z4*/
|
||||
GROUP(dvp_d2, 3, 11), /*z4*/
|
||||
|
||||
GROUP(i2sout_ch23_z5, 3, 26), /*z5*/
|
||||
GROUP(dvp_d3, 3, 11), /*z5*/
|
||||
|
||||
GROUP(iso7816_clk, 4, 9), /*z6*/
|
||||
GROUP(i2sout_ch45, 3, 25), /*z6*/
|
||||
GROUP(dvp_d4, 3, 11), /*z6*/
|
||||
|
||||
|
||||
GROUP(spi_sclk_0, 4, 4),/*z11*/
|
||||
GROUP(spi_miso_0, 4, 3),/*z12*/
|
||||
GROUP(spi_mosi_0, 4, 2),/*z13*/
|
||||
|
||||
GROUP(spdif_in, 3, 21),
|
||||
GROUP(eth_link_led, 4, 25),
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* Bank DV */
|
||||
GROUP(uart_tx_b, 2, 16),
|
||||
GROUP(uart_rx_b, 2, 15),
|
||||
GROUP(uart_cts_b, 2, 14),
|
||||
GROUP(uart_rts_b, 2, 13),
|
||||
|
||||
GROUP(lcd_vs, 3, 4), /* dv24 */
|
||||
GROUP(dmic_in, 2, 7),
|
||||
GROUP(tcon_stv1, 1, 22),
|
||||
GROUP(i2c_sda_a, 1, 15),
|
||||
|
||||
GROUP(i2c_sda_a, 1, 15), /*dv24*/
|
||||
GROUP(i2c_scl_a, 1, 14), /*dv25*/
|
||||
|
||||
GROUP(i2c_sda_b, 1, 13), /*dv26*/
|
||||
GROUP(i2c_scl_b, 1, 12), /*dv27*/
|
||||
|
||||
GROUP(i2c_sda_c, 1, 11), /*dv28*/
|
||||
GROUP(i2c_scl_c, 1, 10), /*dv29*/
|
||||
|
||||
GROUP(i2c_sda_c_1, 1, 17), /*dv18*/
|
||||
GROUP(i2c_scl_c_1, 1, 16), /*dv19*/
|
||||
|
||||
/* Bank BOOT */
|
||||
GROUP(emmc_nand_d07, 7, 31),
|
||||
GROUP(emmc_clk, 7, 30),
|
||||
GROUP(emmc_cmd, 7, 29),
|
||||
GROUP(emmc_ds, 4, 31),
|
||||
|
||||
GROUP(tst_clk_0, 7, 23), /*boot3*/
|
||||
|
||||
GROUP(tst_clk_6, 7, 17), /*boot9*/
|
||||
|
||||
GROUP(nand_ce0, 7, 7), /*boot8*/
|
||||
GROUP(nand_ce1, 7, 6), /*boot9*/
|
||||
GROUP(nand_rb0, 7, 5), /*boot10*/
|
||||
GROUP(nand_ale, 7, 4), /*boot11*/
|
||||
GROUP(nand_cle, 7, 3), /*boot12*/
|
||||
GROUP(nand_wen_clk, 7, 2), /*boot13*/
|
||||
GROUP(nand_ren_wr, 7, 1), /*boot14*/
|
||||
GROUP(nand_dqs, 7, 0), /*boot15*/
|
||||
|
||||
/* Bank CARD */
|
||||
GROUP(sdcard_d1, 6, 5), /*card0*/
|
||||
GROUP(sdcard_d0, 6, 4), /*card1*/
|
||||
GROUP(sdcard_clk, 6, 3), /*card2*/
|
||||
GROUP(sdcard_cmd, 6, 2), /*card3*/
|
||||
GROUP(sdcard_d3, 6, 1), /*card4*/
|
||||
GROUP(sdcard_d2, 6, 0), /*card5*/
|
||||
|
||||
GROUP(uart_tx_ao_a_1, 6, 9), /*card4*/
|
||||
GROUP(uart_rx_ao_a_1, 6, 8), /*card5*/
|
||||
|
||||
GROUP(tst_clk_9, 6, 7), /*card4*/
|
||||
|
||||
GROUP(jtag_tdi_0, 0, 0xff),
|
||||
GROUP(jtag_tdo_0, 0, 0xff),
|
||||
GROUP(jtag_clk_0, 0, 0xff),
|
||||
GROUP(jtag_tms_0, 0, 0xff),
|
||||
GROUP(jtag_tdi_1, 0, 0xff),
|
||||
GROUP(jtag_tdo_1, 0, 0xff),
|
||||
GROUP(jtag_clk_1, 0, 0xff),
|
||||
GROUP(jtag_tms_1, 0, 0xff),
|
||||
};
|
||||
|
||||
|
||||
static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = {
|
||||
MESON_PIN(GPIOAO_0, 0),
|
||||
MESON_PIN(GPIOAO_1, 0),
|
||||
MESON_PIN(GPIOAO_2, 0),
|
||||
MESON_PIN(GPIOAO_3, 0),
|
||||
MESON_PIN(GPIOAO_4, 0),
|
||||
MESON_PIN(GPIOAO_5, 0),
|
||||
MESON_PIN(GPIOAO_6, 0),
|
||||
MESON_PIN(GPIOAO_7, 0),
|
||||
MESON_PIN(GPIOAO_8, 0),
|
||||
MESON_PIN(GPIOAO_9, 0),
|
||||
};
|
||||
|
||||
|
||||
static const unsigned int uart_tx_ao_b_0_pins[] = { PIN(GPIOAO_4, 0) };
|
||||
static const unsigned int uart_rx_ao_b_0_pins[] = { PIN(GPIOAO_5, 0) };
|
||||
|
||||
static const unsigned int uart_tx_ao_b_1_pins[] = { PIN(GPIOAO_0, 0) };
|
||||
static const unsigned int uart_rx_ao_b_1_pins[] = { PIN(GPIOAO_1, 0) };
|
||||
|
||||
|
||||
static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) };
|
||||
static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) };
|
||||
static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) };
|
||||
static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) };
|
||||
|
||||
static const unsigned int pwm_ao_a_pins[] = { PIN(GPIOAO_3, 0) };
|
||||
|
||||
static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
|
||||
static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
|
||||
static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
|
||||
static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
|
||||
|
||||
static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_6, 0) };
|
||||
|
||||
static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, 0) };
|
||||
static const unsigned int remote_output_pins[] = { PIN(GPIOAO_7, 0),
|
||||
/*PIN(GPIOAO_9, 0)*/ };
|
||||
|
||||
static const unsigned int ao_cec_pins[] = { PIN(GPIOAO_8, 0) };
|
||||
static const unsigned int ee_cec_pins[] = { PIN(GPIOAO_8, 0) };
|
||||
static const unsigned int i2sout_ch23_ao8_pins[] = { PIN(GPIOAO_8, 0) };
|
||||
static const unsigned int pwm_ao_a_1_pins[] = { PIN(GPIOAO_8, 0) };
|
||||
|
||||
static const unsigned int spdid_out_1_pins[] = { PIN(GPIOAO_9, 0) };
|
||||
static const unsigned int i2sout_ch45_ao9_pins[] = { PIN(GPIOAO_9, 0) };
|
||||
static const unsigned int pwm_ao_b_1_pins[] = { PIN(GPIOAO_9, 0) };
|
||||
|
||||
static struct meson_pmx_group meson_gxl_aobus_groups[] = {
|
||||
GPIO_GROUP(GPIOAO_0, 0),
|
||||
GPIO_GROUP(GPIOAO_1, 0),
|
||||
GPIO_GROUP(GPIOAO_2, 0),
|
||||
GPIO_GROUP(GPIOAO_3, 0),
|
||||
GPIO_GROUP(GPIOAO_4, 0),
|
||||
GPIO_GROUP(GPIOAO_5, 0),
|
||||
GPIO_GROUP(GPIOAO_6, 0),
|
||||
GPIO_GROUP(GPIOAO_7, 0),
|
||||
GPIO_GROUP(GPIOAO_8, 0),
|
||||
GPIO_GROUP(GPIOAO_9, 0),
|
||||
|
||||
/* bank AO */
|
||||
GROUP(uart_tx_ao_b_1, 0, 26),
|
||||
GROUP(uart_rx_ao_b_1, 0, 25), /*ao_1*/
|
||||
GROUP(uart_tx_ao_a_0, 0, 12), /*ao_0*/
|
||||
GROUP(uart_rx_ao_a_0, 0, 11), /*ao_1*/
|
||||
GROUP(uart_cts_ao_a, 0, 10),
|
||||
GROUP(uart_rts_ao_a, 0, 9),
|
||||
GROUP(uart_cts_ao_b, 0, 8),
|
||||
GROUP(uart_rts_ao_b, 0, 7),
|
||||
GROUP(i2c_sck_ao, 0, 6),
|
||||
GROUP(i2c_sda_ao, 0, 5),
|
||||
GROUP(i2c_slave_sck_ao, 0, 2),
|
||||
GROUP(i2c_slave_sda_ao, 0, 1),
|
||||
|
||||
/* add GPIOAO_3 */
|
||||
GROUP(pwm_ao_a, 0, 22),
|
||||
|
||||
GROUP(uart_tx_ao_b_0, 0, 24), /*ao4*/
|
||||
GROUP(uart_rx_ao_b_0, 0, 23), /*ao5*/
|
||||
|
||||
GROUP(spdif_out, 0, 16),
|
||||
GROUP(pwm_ao_b, 0, 18),
|
||||
|
||||
GROUP(remote_input, 0, 0), /*ao7*/
|
||||
GROUP(remote_output, 0, 21), /*ao7*/
|
||||
|
||||
GROUP(ao_cec, 0, 15),
|
||||
GROUP(ee_cec, 0, 14),
|
||||
GROUP(i2sout_ch23_ao8, 2, 0),
|
||||
GROUP(pwm_ao_a_1, 0, 17),
|
||||
|
||||
GROUP(remote_output, 0, 31),/*ao9*/
|
||||
GROUP(spdid_out_1, 0, 4),
|
||||
GROUP(i2sout_ch45_ao9, 2, 1),
|
||||
GROUP(pwm_ao_b_1, 0, 3),
|
||||
};
|
||||
|
||||
static const char * const gpio_periphs_groups[] = {
|
||||
"GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
|
||||
"GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
|
||||
"GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
|
||||
"GPIOZ_15",
|
||||
|
||||
"GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
|
||||
"GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
|
||||
|
||||
"BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
|
||||
"BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
|
||||
"BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", "BOOT_15",
|
||||
|
||||
"CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
|
||||
"CARD_5", "CARD_6",
|
||||
|
||||
"GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
|
||||
"GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
|
||||
"GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
|
||||
"GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
|
||||
"GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
|
||||
"GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
|
||||
|
||||
"GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
|
||||
"GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
|
||||
"GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
|
||||
"GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18",
|
||||
|
||||
"GPIO_TEST_N",
|
||||
};
|
||||
|
||||
static const char * const emmc_groups[] = {
|
||||
"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
|
||||
};
|
||||
|
||||
static const char * const sdcard_groups[] = {
|
||||
"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
|
||||
"sdcard_cmd", "sdcard_clk",
|
||||
};
|
||||
|
||||
|
||||
static const char * const uart_a_groups[] = {
|
||||
"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
|
||||
};
|
||||
|
||||
static const char * const uart_b_groups[] = {
|
||||
"uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b",
|
||||
};
|
||||
|
||||
static const char * const uart_c_groups[] = {
|
||||
"uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c",
|
||||
};
|
||||
|
||||
static const char * const eth_groups[] = {
|
||||
"eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
|
||||
"eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
|
||||
"eth_rgmii_tx_clk", "eth_tx_en",
|
||||
"eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3",
|
||||
};
|
||||
|
||||
|
||||
static const char * const jtag_groups[] = {
|
||||
"jtag_tdi_0", "jtag_tdo_0", "jtag_clk_0", "jtag_tms_0",
|
||||
"jtag_tdi_1", "jtag_tdo_1", "jtag_clk_1", "jtag_tms_1",
|
||||
};
|
||||
|
||||
static const char * const pwm_e_groups[] = {
|
||||
"pwm_e",
|
||||
};
|
||||
|
||||
|
||||
static const char * const pcm_a_groups[] = {
|
||||
"pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a",
|
||||
};
|
||||
|
||||
static const char * const spdif_out_groups[] = {
|
||||
"spdif_out",
|
||||
};
|
||||
|
||||
|
||||
static const char * const spi_groups[] = {
|
||||
"spi_sclk_0", "spi_miso_0", "spi_mosi_0",
|
||||
"spi_sclk_1", "spi_miso_1", "spi_mosi_1",
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
static const char * const nand_groups[] = {
|
||||
"emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale",
|
||||
"nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs",
|
||||
};
|
||||
|
||||
static const char * const hdmi_hpd_groups[] = {
|
||||
"hdmi_hpd",
|
||||
};
|
||||
|
||||
static const char * const hdmi_ddc_groups[] = {
|
||||
"hdmi_sda", "hdmi_scl",
|
||||
};
|
||||
|
||||
static const char * const i2c_a_groups[] = {
|
||||
"i2c_sda_a", "i2c_scl_a",
|
||||
};
|
||||
|
||||
static const char * const i2c_b_groups[] = {
|
||||
"i2c_sda_b", "i2c_scl_b",
|
||||
};
|
||||
|
||||
static const char * const i2c_c_groups[] = {
|
||||
"i2c_sda_c", "i2c_scl_c",
|
||||
};
|
||||
|
||||
static const char * const i2c_c_1_groups[] = {
|
||||
"i2c_sda_c_1", "i2c_scl_c_1",
|
||||
};
|
||||
|
||||
static const char * const i2c_d_groups[] = {
|
||||
"i2c_sda_d", "i2c_sda_d",
|
||||
};
|
||||
|
||||
static const char * const i2s_groups[] = {
|
||||
"i2s_am_clk", "i2s_ao_clk_out", "i2s_lr_clk_out", "i2sout_ch01",
|
||||
};
|
||||
|
||||
static const char * const sdio_groups[] = {
|
||||
"sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd",
|
||||
};
|
||||
|
||||
|
||||
static struct meson_pmx_func meson_gxl_periphs_functions[] = {
|
||||
FUNCTION(gpio_periphs),
|
||||
FUNCTION(emmc),
|
||||
FUNCTION(sdcard),
|
||||
FUNCTION(uart_a),
|
||||
FUNCTION(uart_b),
|
||||
FUNCTION(uart_c),
|
||||
FUNCTION(eth),
|
||||
FUNCTION(jtag),
|
||||
FUNCTION(pwm_e),
|
||||
FUNCTION(pcm_a),
|
||||
FUNCTION(spdif_out),
|
||||
FUNCTION(i2s),
|
||||
FUNCTION(spi),
|
||||
FUNCTION(i2c_a),
|
||||
FUNCTION(i2c_b),
|
||||
FUNCTION(i2c_c),
|
||||
FUNCTION(i2c_d),
|
||||
FUNCTION(hdmi_ddc),
|
||||
FUNCTION(hdmi_hpd),
|
||||
FUNCTION(nand),
|
||||
FUNCTION(sdio),
|
||||
|
||||
};
|
||||
|
||||
static const char * const gpio_aobus_groups[] = {
|
||||
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
|
||||
"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
|
||||
};
|
||||
|
||||
static const char * const uart_ao_groups[] = {
|
||||
"uart_tx_ao_a_0", "uart_rx_ao_a_0", "uart_cts_ao_a_0",
|
||||
"uart_rts_ao_a_0", "uart_tx_ao_a_1", "uart_rx_ao_a_1",
|
||||
"uart_cts_ao_a_1", "uart_rts_ao_a_1",
|
||||
};
|
||||
|
||||
static const char * const uart_ao_b_groups[] = {
|
||||
"uart_tx_ao_b_0", "uart_rx_ao_b_0", "uart_cts_ao_b_0",
|
||||
"uart_rts_ao_b_0", "uart_tx_ao_b_0", "uart_rx_ao_b_0",
|
||||
"uart_cts_ao_b_0", "uart_rts_ao_b_0",
|
||||
};
|
||||
|
||||
static const char * const i2c_ao_groups[] = {
|
||||
"i2c_sck_ao", "i2c_sda_ao",
|
||||
};
|
||||
|
||||
static const char * const i2c_slave_ao_groups[] = {
|
||||
"i2c_slave_sck_ao", "i2c_slave_sda_ao",
|
||||
};
|
||||
|
||||
static const char * const remote_groups[] = {
|
||||
"remote_input",
|
||||
};
|
||||
|
||||
static const char * const ee_cec_groups[] = {
|
||||
"ee_cec",
|
||||
};
|
||||
|
||||
static const char * const ao_cec_groups[] = {
|
||||
"ao_cec",
|
||||
};
|
||||
static struct meson_pmx_func meson_gxl_aobus_functions[] = {
|
||||
FUNCTION(gpio_aobus),
|
||||
FUNCTION(uart_ao),
|
||||
FUNCTION(uart_ao_b),
|
||||
FUNCTION(i2c_ao),
|
||||
FUNCTION(i2c_slave_ao),
|
||||
FUNCTION(remote),
|
||||
FUNCTION(ee_cec),
|
||||
FUNCTION(ao_cec),
|
||||
};
|
||||
|
||||
static struct meson_bank meson_gxl_periphs_banks[] = {
|
||||
/* name first last pullen pull dir out in */
|
||||
BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_18, EE_OFF),
|
||||
4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
|
||||
|
||||
BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF),
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
|
||||
BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_9, EE_OFF),
|
||||
1, 20, 1, 20, 3, 20, 4, 20, 5, 20),
|
||||
BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF),
|
||||
3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
|
||||
BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF),
|
||||
2, 20, 2, 20, 6, 20, 7, 20, 8, 20),
|
||||
BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF),
|
||||
2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
|
||||
BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_1, EE_OFF),
|
||||
3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
|
||||
};
|
||||
|
||||
static struct meson_bank meson_gxl_aobus_banks[] = {
|
||||
/* name first last pullen pull dir out in */
|
||||
BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_9, 0),
|
||||
0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
|
||||
};
|
||||
|
||||
static struct meson_domain_data meson_gxl_periphs_domain_data = {
|
||||
.name = "periphs-banks",
|
||||
.banks = meson_gxl_periphs_banks,
|
||||
.num_banks = ARRAY_SIZE(meson_gxl_periphs_banks),
|
||||
.pin_base = 10,
|
||||
.num_pins = 101,
|
||||
};
|
||||
|
||||
static struct meson_domain_data meson_gxl_aobus_domain_data = {
|
||||
.name = "aobus-banks",
|
||||
.banks = meson_gxl_aobus_banks,
|
||||
.num_banks = ARRAY_SIZE(meson_gxl_aobus_banks),
|
||||
.pin_base = 0,
|
||||
.num_pins = 10,
|
||||
};
|
||||
|
||||
struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
|
||||
.pins = meson_gxl_periphs_pins,
|
||||
.groups = meson_gxl_periphs_groups,
|
||||
.funcs = meson_gxl_periphs_functions,
|
||||
.domain_data = &meson_gxl_periphs_domain_data,
|
||||
.num_pins = ARRAY_SIZE(meson_gxl_periphs_pins),
|
||||
.num_groups = ARRAY_SIZE(meson_gxl_periphs_groups),
|
||||
.num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions),
|
||||
};
|
||||
|
||||
struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
|
||||
.pins = meson_gxl_aobus_pins,
|
||||
.groups = meson_gxl_aobus_groups,
|
||||
.funcs = meson_gxl_aobus_functions,
|
||||
.domain_data = &meson_gxl_aobus_domain_data,
|
||||
.num_pins = ARRAY_SIZE(meson_gxl_aobus_pins),
|
||||
.num_groups = ARRAY_SIZE(meson_gxl_aobus_groups),
|
||||
.num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions),
|
||||
};
|
||||
137
include/dt-bindings/gpio/gxl.h
Normal file
137
include/dt-bindings/gpio/gxl.h
Normal file
@@ -0,0 +1,137 @@
|
||||
/*
|
||||
* include/dt-bindings/gpio/gxl.h
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_MESON_GXM_GPIO_H
|
||||
#define _DT_BINDINGS_MESON_GXM_GPIO_H
|
||||
|
||||
#define GPIOAO_0 0
|
||||
#define GPIOAO_1 1
|
||||
#define GPIOAO_2 2
|
||||
#define GPIOAO_3 3
|
||||
#define GPIOAO_4 4
|
||||
#define GPIOAO_5 5
|
||||
#define GPIOAO_6 6
|
||||
#define GPIOAO_7 7
|
||||
#define GPIOAO_8 8
|
||||
#define GPIOAO_9 9
|
||||
|
||||
#define GPIOZ_0 0
|
||||
#define GPIOZ_1 1
|
||||
#define GPIOZ_2 2
|
||||
#define GPIOZ_3 3
|
||||
#define GPIOZ_4 4
|
||||
#define GPIOZ_5 5
|
||||
#define GPIOZ_6 6
|
||||
#define GPIOZ_7 7
|
||||
#define GPIOZ_8 8
|
||||
#define GPIOZ_9 9
|
||||
#define GPIOZ_10 10
|
||||
#define GPIOZ_11 11
|
||||
#define GPIOZ_12 12
|
||||
#define GPIOZ_13 13
|
||||
#define GPIOZ_14 14
|
||||
#define GPIOZ_15 15
|
||||
#define GPIOH_0 16
|
||||
#define GPIOH_1 17
|
||||
#define GPIOH_2 18
|
||||
#define GPIOH_3 19
|
||||
#define GPIOH_4 20
|
||||
#define GPIOH_5 21
|
||||
#define GPIOH_6 22
|
||||
#define GPIOH_7 23
|
||||
#define GPIOH_8 24
|
||||
#define GPIOH_9 25
|
||||
#define BOOT_0 26
|
||||
#define BOOT_1 27
|
||||
#define BOOT_2 28
|
||||
#define BOOT_3 29
|
||||
#define BOOT_4 30
|
||||
#define BOOT_5 31
|
||||
#define BOOT_6 32
|
||||
#define BOOT_7 33
|
||||
#define BOOT_8 34
|
||||
#define BOOT_9 35
|
||||
#define BOOT_10 36
|
||||
#define BOOT_11 37
|
||||
#define BOOT_12 38
|
||||
#define BOOT_13 39
|
||||
#define BOOT_14 40
|
||||
#define BOOT_15 41
|
||||
#define CARD_0 42
|
||||
#define CARD_1 43
|
||||
#define CARD_2 44
|
||||
#define CARD_3 45
|
||||
#define CARD_4 46
|
||||
#define CARD_5 47
|
||||
#define CARD_6 48
|
||||
#define GPIODV_0 49
|
||||
#define GPIODV_1 50
|
||||
#define GPIODV_2 51
|
||||
#define GPIODV_3 52
|
||||
#define GPIODV_4 53
|
||||
#define GPIODV_5 54
|
||||
#define GPIODV_6 55
|
||||
#define GPIODV_7 56
|
||||
#define GPIODV_8 57
|
||||
#define GPIODV_9 58
|
||||
#define GPIODV_10 59
|
||||
#define GPIODV_11 60
|
||||
#define GPIODV_12 61
|
||||
#define GPIODV_13 62
|
||||
#define GPIODV_14 63
|
||||
#define GPIODV_15 64
|
||||
#define GPIODV_16 65
|
||||
#define GPIODV_17 66
|
||||
#define GPIODV_18 67
|
||||
#define GPIODV_19 68
|
||||
#define GPIODV_20 69
|
||||
#define GPIODV_21 70
|
||||
#define GPIODV_22 71
|
||||
#define GPIODV_23 72
|
||||
#define GPIODV_24 73
|
||||
#define GPIODV_25 74
|
||||
#define GPIODV_26 75
|
||||
#define GPIODV_27 76
|
||||
#define GPIODV_28 77
|
||||
#define GPIODV_29 78
|
||||
#define GPIOX_0 79
|
||||
#define GPIOX_1 80
|
||||
#define GPIOX_2 81
|
||||
#define GPIOX_3 82
|
||||
#define GPIOX_4 83
|
||||
#define GPIOX_5 84
|
||||
#define GPIOX_6 85
|
||||
#define GPIOX_7 86
|
||||
#define GPIOX_8 87
|
||||
#define GPIOX_9 88
|
||||
#define GPIOX_10 89
|
||||
#define GPIOX_11 90
|
||||
#define GPIOX_12 91
|
||||
#define GPIOX_13 92
|
||||
#define GPIOX_14 93
|
||||
#define GPIOX_15 94
|
||||
#define GPIOX_16 95
|
||||
#define GPIOX_17 96
|
||||
#define GPIOX_18 97
|
||||
#define GPIOCLK_0 98
|
||||
#define GPIOCLK_1 99
|
||||
#define GPIO_TEST_N 100
|
||||
|
||||
#define AO 0x10
|
||||
#define AO2 0x11
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user