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arm64: dts: allwinner: a64: Add L2 cache nodes

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Current kernels complain when booting on an A64 Soc:
....
[    1.904297] cacheinfo: Unable to detect cache hierarchy for CPU 0
....
Not a real biggie on this flat topology, but also easy enough to fix.

Add the L2 cache node and let each CPU point to it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Andre Przywara
2018-07-30 13:31:19 +01:00
committed by Chen-Yu Tsai
parent fcddd1f609
commit 39defc8132
1 changed files with 9 additions and 0 deletions
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9
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -88,6 +88,7 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@@ -95,6 +96,7 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@@ -102,6 +104,7 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@@ -109,6 +112,12 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
next-level-cache = <&L2>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};