ODROID-N2: Merge amlogic BSP 2019.0415 (fix build err)

Change-Id: I1987cce33154a36658b066f44ce1463d267d0043
2026-06-10 04:48:04 +09:00 · 2019-05-17 14:56:01 +09:00
parent b157b2fb93
commit 3a03ee7c2e
9 changed files with 272 additions and 148 deletions
--- a/drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h
+++ b/drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h
@@ -918,6 +918,172 @@ static struct am_regs_s cmreg_enhancement = {
 	}
 };

+/*sr0 sharpness reg*/
+struct am_regs_s sr0reg_cvbs = {
+	109,
+	{
+	{REG_TYPE_VCBUS, SHARP0_SHARP_HVSIZE, 0xffffffff, 0x02d00240},
+	{REG_TYPE_VCBUS, SHARP0_SHARP_HVBLANK_NUM, 0xffffffff, 0x00001e58},
+	{REG_TYPE_VCBUS, SHARP0_NR_GAUSSIAN_MODE, 0xffffffff, 0x00000010},
+	{REG_TYPE_VCBUS, SHARP0_PKOSHT_VSLUMA_LUT_L, 0xffffffff, 0x56667ac8},
+	{REG_TYPE_VCBUS, SHARP0_PKOSHT_VSLUMA_LUT_H, 0xffffffff, 0x00000004},
+	{REG_TYPE_VCBUS, SHARP0_PK_CON_2CIRHPGAIN_TH_RATE,
+		0xffffffff, 0x14323218},
+	{REG_TYPE_VCBUS, SHARP0_PK_CON_2CIRHPGAIN_LIMIT,
+		0xffffffff, 0x50845e00},
+	{REG_TYPE_VCBUS, SHARP0_PK_CON_2CIRBPGAIN_TH_RATE,
+		0xffffffff, 0x14323218},
+	{REG_TYPE_VCBUS, SHARP0_PK_CON_2CIRBPGAIN_LIMIT,
+		0xffffffff, 0x508d5000},
+	{REG_TYPE_VCBUS, SHARP0_PK_CON_2DRTHPGAIN_TH_RATE,
+		0xffffffff, 0x14323218},
+	{REG_TYPE_VCBUS, SHARP0_PK_CON_2DRTHPGAIN_LIMIT,
+		0xffffffff, 0x3d3d1f00},
+	{REG_TYPE_VCBUS, SHARP0_PK_CON_2DRTBPGAIN_TH_RATE,
+		0xffffffff, 0x14323218},
+	{REG_TYPE_VCBUS, SHARP0_PK_CON_2DRTBPGAIN_LIMIT,
+		0xffffffff, 0x38390c00},
+	{REG_TYPE_VCBUS, SHARP0_PK_CIRFB_LPF_MODE, 0xffffffff, 0x22202220},
+	{REG_TYPE_VCBUS, SHARP0_PK_DRTFB_LPF_MODE, 0xffffffff, 0x22202220},
+	{REG_TYPE_VCBUS, SHARP0_PK_CIRFB_HP_CORING, 0xffffffff, 0x00020202},
+	{REG_TYPE_VCBUS, SHARP0_PK_CIRFB_BP_CORING, 0xffffffff, 0x00020202},
+	{REG_TYPE_VCBUS, SHARP0_PK_DRTFB_HP_CORING, 0xffffffff, 0x00020202},
+	{REG_TYPE_VCBUS, SHARP0_PK_DRTFB_BP_CORING, 0xffffffff, 0x00020202},
+	{REG_TYPE_VCBUS, SHARP0_PK_CIRFB_BLEND_GAIN, 0xffffffff, 0x38402840},
+	{REG_TYPE_VCBUS, SHARP0_NR_ALPY_SSD_GAIN_OFST,
+		0xffffffff, 0x0000103e},
+	{REG_TYPE_VCBUS, SHARP0_NR_ALP0Y_ERR2CURV_TH_RATE,
+		0xffffffff, 0x0a195040},
+	{REG_TYPE_VCBUS, SHARP0_NR_ALP0Y_ERR2CURV_LIMIT,
+		0xffffffff, 0x3f003f00},
+	{REG_TYPE_VCBUS, SHARP0_NR_ALP0C_ERR2CURV_TH_RATE,
+		0xffffffff, 0x0a195040},
+	{REG_TYPE_VCBUS, SHARP0_NR_ALP0C_ERR2CURV_LIMIT,
+		0xffffffff, 0x3f003f00},
+	{REG_TYPE_VCBUS, SHARP0_NR_ALP0_MIN_MAX, 0xffffffff, 0x003f003f},
+	{REG_TYPE_VCBUS, SHARP0_NR_ALP1_MIERR_CORING,
+		0xffffffff, 0x00000003},
+	{REG_TYPE_VCBUS, SHARP0_NR_ALP1_ERR2CURV_TH_RATE,
+		0xffffffff, 0x00180014},
+	{REG_TYPE_VCBUS, SHARP0_NR_ALP1_ERR2CURV_LIMIT,
+		0xffffffff, 0x00103f00},
+	{REG_TYPE_VCBUS, SHARP0_NR_ALP1_MIN_MAX, 0xffffffff, 0x003f003f},
+	{REG_TYPE_VCBUS, SHARP0_PK_ALP2_MIERR_CORING,
+		0xffffffff, 0x00010001},
+	{REG_TYPE_VCBUS, SHARP0_PK_ALP2_ERR2CURV_TH_RATE,
+		0xffffffff, 0x0018000a},
+	{REG_TYPE_VCBUS, SHARP0_PK_ALP2_ERR2CURV_LIMIT,
+		0xffffffff, 0x00402000},
+	{REG_TYPE_VCBUS, SHARP0_PK_ALP2_MIN_MAX, 0xffffffff, 0x0000003f},
+	{REG_TYPE_VCBUS, SHARP0_PK_FINALGAIN_HP_BP,
+		0xffffffff, 0x00001414},
+	{REG_TYPE_VCBUS, SHARP0_PK_OS_HORZ_CORE_GAIN,
+		0xffffffff, 0x08140214},
+	{REG_TYPE_VCBUS, SHARP0_PK_OS_VERT_CORE_GAIN,
+		0xffffffff, 0x08140214},
+	{REG_TYPE_VCBUS, SHARP0_PK_OS_ADPT_MISC,
+		0xffffffff, 0x2806c814},
+	{REG_TYPE_VCBUS, SHARP0_PK_OS_STATIC, 0xffffffff, 0x2203f03f},
+	{REG_TYPE_VCBUS, SHARP0_PK_NR_ENABLE, 0xffffffff, 0x00000000},
+	{REG_TYPE_VCBUS, SHARP0_PK_DRT_SAD_MISC, 0xffffffff, 0x12120018},
+	{REG_TYPE_VCBUS, SHARP0_NR_TI_DNLP_BLEND, 0xffffffff, 0x00000407},
+	{REG_TYPE_VCBUS, SHARP0_TI_DIR_CORE_ALPHA, 0xffffffff, 0x0a00003f},
+	{REG_TYPE_VCBUS, SHARP0_CTI_DIR_ALPHA, 0xffffffff, 0x0400003f},
+	{REG_TYPE_VCBUS, SHARP0_LTI_CTI_DF_GAIN, 0xffffffff, 0x0c0c0c0c},
+	{REG_TYPE_VCBUS, SHARP0_LTI_CTI_DIR_AC_DBG, 0xffffffff, 0x56ee0000},
+	{REG_TYPE_VCBUS, SHARP0_HCTI_FLT_CLP_DC, 0xffffffff, 0x05555300},
+	{REG_TYPE_VCBUS, SHARP0_HCTI_BST_GAIN, 0xffffffff, 0x050a0a00},
+	{REG_TYPE_VCBUS, SHARP0_HCTI_BST_CORE, 0xffffffff, 0x03030303},
+	{REG_TYPE_VCBUS, SHARP0_HCTI_CON_2_GAIN_0, 0xffffffff, 0x24193c05},
+	{REG_TYPE_VCBUS, SHARP0_HCTI_CON_2_GAIN_1, 0xffffffff, 0x4b055014},
+	{REG_TYPE_VCBUS, SHARP0_HCTI_OS_MARGIN, 0xffffffff, 0x00000000},
+	{REG_TYPE_VCBUS, SHARP0_HLTI_FLT_CLP_DC, 0xffffffff, 0x00152100},
+	{REG_TYPE_VCBUS, SHARP0_HLTI_BST_GAIN, 0xffffffff, 0x06060600},
+	{REG_TYPE_VCBUS, SHARP0_HLTI_BST_CORE, 0xffffffff, 0x03030303},
+	{REG_TYPE_VCBUS, SHARP0_HLTI_CON_2_GAIN_0, 0xffffffff, 0x24193c05},
+	{REG_TYPE_VCBUS, SHARP0_HLTI_CON_2_GAIN_1, 0xffffffff, 0x66635e24},
+	{REG_TYPE_VCBUS, SHARP0_HLTI_OS_MARGIN, 0xffffffff, 0x00000000},
+	{REG_TYPE_VCBUS, SHARP0_VLTI_FLT_CON_CLP, 0xffffffff, 0x00002a94},
+	{REG_TYPE_VCBUS, SHARP0_VLTI_BST_GAIN, 0xffffffff, 0x00202020},
+	{REG_TYPE_VCBUS, SHARP0_VLTI_BST_CORE, 0xffffffff, 0x00050503},
+	{REG_TYPE_VCBUS, SHARP0_VLTI_CON_2_GAIN_0, 0xffffffff, 0x193c0560},
+	{REG_TYPE_VCBUS, SHARP0_VLTI_CON_2_GAIN_1, 0xffffffff, 0x5f501400},
+	{REG_TYPE_VCBUS, SHARP0_VCTI_FLT_CON_CLP, 0xffffffff, 0x00002a94},
+	{REG_TYPE_VCBUS, SHARP0_VCTI_BST_GAIN, 0xffffffff, 0x00101010},
+	{REG_TYPE_VCBUS, SHARP0_VCTI_BST_CORE, 0xffffffff, 0x00050503},
+	{REG_TYPE_VCBUS, SHARP0_VCTI_CON_2_GAIN_0, 0xffffffff, 0x193c0560},
+	{REG_TYPE_VCBUS, SHARP0_VCTI_CON_2_GAIN_1, 0xffffffff, 0x5f501400},
+	{REG_TYPE_VCBUS, SHARP0_SHARP_3DLIMIT, 0xffffffff, 0x03c0021c},
+	/*{REG_TYPE_VCBUS, SHARP0_SHARP_SR2_CTRL, 0xffffffff, 0x0018103c},*/
+	{REG_TYPE_VCBUS, SHARP0_SHARP_SR2_YBIC_HCOEF0,
+		0xffffffff, 0x00004000},
+	{REG_TYPE_VCBUS, SHARP0_SHARP_SR2_YBIC_HCOEF1,
+		0xffffffff, 0xfc2424fc},
+	{REG_TYPE_VCBUS, SHARP0_SHARP_SR2_CBIC_HCOEF0,
+		0xffffffff, 0x00004000},
+	{REG_TYPE_VCBUS, SHARP0_SHARP_SR2_CBIC_HCOEF1,
+		0xffffffff, 0xfc2424fc},
+	{REG_TYPE_VCBUS, SHARP0_SHARP_SR2_YBIC_VCOEF0,
+		0xffffffff, 0x00004000},
+	{REG_TYPE_VCBUS, SHARP0_SHARP_SR2_YBIC_VCOEF1,
+		0xffffffff, 0xfc2424fc},
+	{REG_TYPE_VCBUS, SHARP0_SHARP_SR2_CBIC_VCOEF0,
+		0xffffffff, 0x00004000},
+	{REG_TYPE_VCBUS, SHARP0_SHARP_SR2_CBIC_VCOEF1,
+		0xffffffff, 0xfc2424fc},
+	{REG_TYPE_VCBUS, SHARP0_SHARP_SR2_MISC, 0xffffffff, 0x00000000},
+	{REG_TYPE_VCBUS, SHARP0_SR3_SAD_CTRL, 0xffffffff, 0x060606ff},
+	{REG_TYPE_VCBUS, SHARP0_SR3_PK_CTRL0, 0xffffffff, 0x00000ffc},
+	{REG_TYPE_VCBUS, SHARP0_SR3_PK_CTRL1, 0xffffffff, 0x112020cc},
+	{REG_TYPE_VCBUS, SHARP0_DEJ_CTRL, 0xffffffff, 0x0000000f},
+	{REG_TYPE_VCBUS, SHARP0_DEJ_ALPHA, 0xffffffff, 0x0f0f4646},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DRTLPF_EN, 0xffffffff, 0x00000037},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DRTLPF_ALPHA_0,
+		0xffffffff, 0x0405050c},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DRTLPF_ALPHA_1,
+		0xffffffff, 0x01040708},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DRTLPF_ALPHA_2,
+		0xffffffff, 0x00000000},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DRTLPF_ALPHA_OFST,
+		0xffffffff, 0x000e000e},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DERING_CTRL,
+		0xffffffff, 0x1392281c},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DERING_LUMA2PKGAIN_0TO3,
+		0xffffffff, 0xffffc81e},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DERING_LUMA2PKGAIN_4TO6,
+		0xffffffff, 0x001832ff},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DERING_LUMA2PKOS_0TO3,
+		0xffffffff, 0xffffc81e},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DERING_LUMA2PKOS_4TO6,
+		0xffffffff, 0x001832ff},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DERING_GAINVS_MADSAD,
+		0xffffffff, 0x00000048},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DERING_GAINVS_VR2MAX,
+		0xffffffff, 0xffffec20},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DERING_PARAM0,
+		0xffffffff, 0x000a2010},
+	{REG_TYPE_VCBUS, SHARP0_SR3_DRTLPF_THETA,
+		0xffffffff, 0xfec96420},
+	{REG_TYPE_VCBUS, SHARP0_SATPRT_CTRL, 0xffffffff, 0x00054006},
+	{REG_TYPE_VCBUS, SHARP0_SATPRT_DIVM, 0xffffffff, 0x00808080},
+	{REG_TYPE_VCBUS, SHARP0_DB_FLT_CTRL, 0xffffffff, 0x06e222fa},
+	{REG_TYPE_VCBUS, SHARP0_DB_FLT_YC_THRD,
+		0xffffffff, 0x97659765},
+	{REG_TYPE_VCBUS, SHARP0_DB_FLT_RANDLUT,
+		0xffffffff, 0x00249249},
+	{REG_TYPE_VCBUS, SHARP0_DB_FLT_PXI_THRD,
+		0xffffffff, 0x00000000},
+	{REG_TYPE_VCBUS, SHARP0_DB_FLT_SEED_Y, 0xffffffff, 0x60a52f20},
+	{REG_TYPE_VCBUS, SHARP0_DB_FLT_SEED_U, 0xffffffff, 0x60a52f27},
+	{REG_TYPE_VCBUS, SHARP0_DB_FLT_SEED_V, 0xffffffff, 0x60a52f22},
+	{REG_TYPE_VCBUS, SHARP0_PKGAIN_VSLUMA_LUT_L,
+		0xffffffff, 0x56667ac8},
+	{REG_TYPE_VCBUS, SHARP0_PKGAIN_VSLUMA_LUT_H,
+		0xffffffff, 0x00000004},
+	{0}
+	}
+};
+
 /*sr1 sharpness reg*/
 struct am_regs_s sr1reg_sd_scale = {
 	109,
--- a/sound/soc/amlogic/auge/ddr_mngr.c
+++ b/sound/soc/amlogic/auge/ddr_mngr.c
@@ -494,8 +494,9 @@ unsigned int aml_toddr_read1(struct toddr *to)
 	unsigned int reg_base = to->reg_base;
 	unsigned int reg;

-	reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL0, reg_base);
-	aml_audiobus_update_bits(actrl,	reg, 1<<30, enable<<30);
+	reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL1, reg_base);
+
+	return aml_audiobus_read(actrl, reg);
 }

 void aml_toddr_write1(struct toddr *to, unsigned int val)
@@ -577,7 +578,7 @@ static void aml_resample_enable(
 	pr_info("toddr %d selects data to %s resample_%c for module:%s\n",
 		to->fifo_id,
 		enable ? "enable" : "disable",
-		(p_attach_resample->id == 0) ? 'a' : 'b',
+		(p_attach_resample->id == RESAMPLE_A) ? 'a' : 'b',
 		toddr_src_get_str(p_attach_resample->attach_module)
 		);

@@ -1010,8 +1011,8 @@ int aml_check_sharebuffer_valid(struct frddr *fr, int ss_sel)
 			&& (frddrs[i].fifo_id != current_fifo_id)
 			&& (frddrs[i].dest == ss_sel)) {

-			pr_info(" frddr:%d, ss_sel:%d used, invalid for share buffer\n",
-				i,
+			pr_debug("%s, ss_sel:%d used, not for share buffer at same time\n",
+				__func__,
 				ss_sel);
 			ret = 0;
 			break;
@@ -1239,69 +1240,14 @@ void aml_frddr_select_dst(struct frddr *fr, enum frddr_dest dst)
 void aml_frddr_select_dst_ss(struct frddr *fr,
 	enum frddr_dest dst, int sel, bool enable)
 {
-	struct aml_audio_controller *actrl = fr->actrl;
-	unsigned int reg_base = fr->reg_base;
-	unsigned int reg, ss_valid;
-
-	ss_valid = aml_check_sharebuffer_valid(fr, dst);
+	unsigned int ss_valid = aml_check_sharebuffer_valid(fr, dst);

 	/* same source en */
 	if (fr->chipinfo
 		&& fr->chipinfo->same_src_fn
-		&& ss_valid) {
-		int s_v = 0, s_m = 0;
-
-			if (fr->chipinfo
-				&& fr->chipinfo->src_sel_ctrl) {
-				reg = calc_frddr_address(EE_AUDIO_FRDDR_A_CTRL2,
-						reg_base);
-
-				switch (sel) {
-				case 1:
-					s_m = 0x17 << 8;
-					s_v = enable ?
-						(dst << 8 | 1 << 12) : 0 << 8;
-					break;
-				case 2:
-					s_m = 0x17 << 16;
-					s_v = enable ?
-						(dst << 16 | 1 << 20) : 0 << 16;
-					break;
-				default:
-					pr_warn_once("sel :%d is not supported for same source\n",
-						sel);
-					break;
-				}
-				s_m |= 0xff << 24;
-				if (enable)
-					s_v |= (fr->channels - 1) << 24;
-				else
-					s_v |= 0x0 << 24;
-			} else {
-				reg = calc_frddr_address(EE_AUDIO_FRDDR_A_CTRL0,
-						reg_base);
-
-				switch (sel) {
-				case 1:
-					s_m = 0xf << 4;
-					s_v = enable ?
-						(dst << 4 | 1 << 7) : 0 << 4;
-					break;
-				case 2:
-					s_m = 0xf << 8;
-					s_v = enable ?
-						(dst << 8 | 1 << 11) : 0 << 8;
-					break;
-				default:
-					pr_warn_once("sel :%d is not supported for same source\n",
-						sel);
-					break;
-				}
-			}
-			pr_debug("%s sel:%d, dst_src:%d\n",
-				__func__, sel, dst);
-			aml_audiobus_update_bits(actrl, reg, s_m, s_v);
-	}
+		&& ss_valid
+	)
+		frddr_set_sharebuffer_enable(fr, dst, sel, enable);
 }

 void aml_frddr_set_fifos(struct frddr *fr,
@@ -1482,7 +1428,7 @@ static const char *const toddr_src_sel_texts[] = {
 	"TDMIN_A", "TDMIN_B", "TDMIN_C", "SPDIFIN",
 	"PDMIN", "FRATV", "TDMIN_LB", "LOOPBACK_A",
 	"FRHDMIRX", "LOOPBACK_B", "SPDIFIN_LB",
-	"EARCRX_DMAC", "RESERVED", "RESERVED", "RESERVED",
+	"EARCRX_DMAC", "RESERVED_0", "RESERVED_1", "RESERVED_2",
 	"VAD"
 };

--- a/sound/soc/amlogic/auge/ddr_mngr.h
+++ b/sound/soc/amlogic/auge/ddr_mngr.h
@@ -42,19 +42,29 @@ enum ddr_types {
 * from tl1, add new source FRATV, FRHDMIRX, LOOPBACK_B, SPDIFIN_LB, VAD
 */
 enum toddr_src {
-	TDMIN_A,
-	TDMIN_B,
-	TDMIN_C,
-	SPDIFIN,
-	PDMIN,
-	FRATV, /* NONE for axg, g12a, g12b */
-	TDMIN_LB,
-	LOOPBACK_A,
-	FRHDMIRX, /* from tl1 chipset*/
-	LOOPBACK_B,
-	SPDIFIN_LB,
-	EARCRX_DMAC, /* from sm1 chipset */
-	VAD,
+	TODDR_INVAL = -1,
+	TDMIN_A = 0,
+	TDMIN_B = 1,
+	TDMIN_C = 2,
+	SPDIFIN = 3,
+	PDMIN = 4,
+	FRATV = 5, /* NONE for axg, g12a, g12b */
+	TDMIN_LB = 6,
+	LOOPBACK_A = 7,
+	FRHDMIRX = 8, /* from tl1 chipset*/
+	LOOPBACK_B = 9,
+	SPDIFIN_LB = 10,
+	EARCRX_DMAC = 11,/* from sm1 chipset */
+	RESERVED_0 = 12,
+	RESERVED_1 = 13,
+	RESERVED_2 = 14,
+	VAD = 15,
+	TODDR_SRC_MAX = 16
+};
+
+enum resample_idx {
+	RESAMPLE_A,
+	RESAMPLE_B
 };

 enum resample_src {
--- a/sound/soc/amlogic/auge/resample.c
+++ b/sound/soc/amlogic/auge/resample.c
@@ -286,13 +286,10 @@ int resample_set(enum resample_idx id, enum samplerate_index index)
 #endif
 	p_resample->asrc_rate_idx = index;

-	pr_info("%s resample_%c %s\n",
-		__func__,
-		(id == 0) ? 'a' : 'b',
-		auge_resample_texts[index]);
-
-	if (audio_resample_set(p_resample, (bool)index, resample_rate))
-		return 0;
+	resample_rate = resample_idx2rate(index);
+	ret = audio_resample_set(p_resample, (bool)index, resample_rate);
+	if (ret)
+		return ret;

 	if (index == RATE_OFF)
 		resample_disable(p_resample->id);
--- a/sound/soc/amlogic/auge/sharebuffer.c
+++ b/sound/soc/amlogic/auge/sharebuffer.c
@@ -36,7 +36,8 @@ static int sharebuffer_spdifout_prepare(struct snd_pcm_substream *substream,
 		aml_frddr_get_fifo_id(fr),
 		bit_depth,
 		runtime->channels,
-		true);
+		true,
+		lane_i2s);

 	/* spdif to hdmitx */
 	spdifout_to_hdmitx_ctrl(spdif_id);
@@ -63,7 +64,7 @@ static int sharebuffer_spdifout_free(struct snd_pcm_substream *substream,
 			aml_frddr_get_fifo_id(fr),
 			bit_depth,
 			runtime->channels,
-			false);
+			false, 0);

 	return 0;
 }
@@ -95,7 +96,7 @@ int sharebuffer_prepare(struct snd_pcm_substream *substream,
 	} else if (samesource_sel < 5) {
 		/* same source with spdif a/b */
 		sharebuffer_spdifout_prepare(substream,
-			fr, samesource_sel - 3);
+			fr, samesource_sel - 3, lane_i2s);
 	}

 	/* frddr, share buffer, src_sel1 */
--- a/sound/soc/amlogic/auge/spdif.c
+++ b/sound/soc/amlogic/auge/spdif.c
@@ -39,7 +39,6 @@
 #include "audio_utils.h"
 #include "resample.h"
 #include "resample_hw.h"
-#include "spdif.h"

 #define DRV_NAME "snd_spdif"

@@ -80,7 +79,7 @@ struct aml_spdif {
 	/* external connect */
 	struct extcon_dev *edev;

-	enum SPDIF_ID id;
+	unsigned int id;
 	struct spdif_chipinfo *chipinfo;
 	unsigned int clk_cont; /* CONTINUOUS CLOCK */

@@ -158,20 +157,6 @@ static const char *const spdifin_samplerate[] = {
 	"192000"
 };

-struct aml_spdif *spdif_priv[SPDIF_ID_CNT];
-int spdif_set_audio_clk(enum SPDIF_ID id,
-		struct clk *clk_src, int rate, bool same)
-{
-	if (spdif_priv[id]->on && same) {
-		pr_debug("spdif priority");
-		return 0;
-	}
-
-	clk_set_parent(spdif_priv[id]->clk_spdifout, clk_src);
-	clk_set_rate(spdif_priv[id]->clk_spdifout, rate);
-	return 0;
-}
-
 static int spdifin_samplerate_get_enum(struct snd_kcontrol *kcontrol,
 			struct snd_ctl_elem_value *ucontrol)
 {
@@ -685,7 +670,6 @@ static void spdifin_status_event(struct aml_spdif *p_spdif)
 			if (!spdifin_check_audiotype_by_sw(p_spdif))
 				resample_set(p_spdif->asrc_id, RATE_OFF);
 #endif
-#endif
 #endif
 		}
 		if (intrpt_status & 0x10)
@@ -763,7 +747,6 @@ static int aml_spdif_open(struct snd_pcm_substream *substream)
 	snd_soc_set_runtime_hwparams(substream, &aml_spdif_hardware);

 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
-		p_spdif->on = 1;
 		p_spdif->fddr = aml_audio_register_frddr(dev,
 			p_spdif->actrl,
 			aml_spdif_ddr_isr, substream);
@@ -809,7 +792,6 @@ static int aml_spdif_close(struct snd_pcm_substream *substream)

 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 		aml_audio_unregister_frddr(p_spdif->dev, substream);
-		p_spdif->on = 0;
 	} else {
 		aml_audio_unregister_toddr(p_spdif->dev, substream);
 		free_irq(p_spdif->irq_spdifin, p_spdif);
@@ -823,7 +805,7 @@ static int aml_spdif_close(struct snd_pcm_substream *substream)
 		}

 		/* clear extcon status */
-		if (p_spdif->id == SPDIF_A) {
+		if (p_spdif->id == 0) {
 			extcon_set_state(p_spdif->edev,
 				EXTCON_SPDIFIN_SAMPLERATE, 0);

@@ -969,7 +951,7 @@ static int aml_spdif_new(struct snd_soc_pcm_runtime *rtd)

 	pr_debug("%s spdif_%s, clk continuous:%d\n",
 		__func__,
-		(p_spdif->id == SPDIF_A) ? "a":"b",
+		(p_spdif->id == 0) ? "a":"b",
 		p_spdif->clk_cont);

 	/* keep frddr when probe, after spdif_frddr_init done
@@ -1025,7 +1007,7 @@ static int aml_dai_spdif_startup(

 		if (p_spdif->clk_cont) {
 			pr_info("spdif_%s keep clk continuous\n",
-				(p_spdif->id == SPDIF_A) ? "a":"b");
+				(p_spdif->id == 0) ? "a":"b");
 			return 0;
 		}
 		/* enable clock gate */
@@ -1098,7 +1080,7 @@ static void aml_dai_spdif_shutdown(
 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 		if (p_spdif->clk_cont) {
 			pr_info("spdif_%s keep clk continuous\n",
-				(p_spdif->id == SPDIF_A) ? "a":"b");
+				(p_spdif->id == 0) ? "a":"b");
 			return;
 		}

@@ -1109,7 +1091,7 @@ static void aml_dai_spdif_shutdown(
 #ifdef __SPDIFIN_AUDIO_TYPE_HW__
 		/* resample disabled, by hw */
 		if (!spdifin_check_audiotype_by_sw(p_spdif))
-			resample_set(p_spdif->asrc_id, 0);
+			resample_set(p_spdif->asrc_id, RATE_OFF);
 #endif
 		clk_disable_unprepare(p_spdif->clk_spdifin);
 		clk_disable_unprepare(p_spdif->fixed_clk);
@@ -1135,10 +1117,10 @@ static int aml_dai_spdif_prepare(
 		struct iec958_chsts chsts;

 		switch (p_spdif->id) {
-		case SPDIF_A:
+		case 0:
 			dst = SPDIFOUT_A;
 			break;
-		case SPDIF_B:
+		case 1:
 			dst = SPDIFOUT_B;
 			break;
 		default:
@@ -1287,9 +1269,6 @@ static int aml_dai_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 			dev_info(substream->pcm->card->dev, "S/PDIF Playback disable\n");
-			memset(substream->runtime->dma_area,
-				0, substream->runtime->dma_bytes);
-			mdelay(3);
 			aml_frddr_enable(p_spdif->fddr, 0);
 		} else {
 			dev_info(substream->pcm->card->dev, "S/PDIF Capture disable\n");
@@ -1360,10 +1339,8 @@ static void aml_set_spdifclk(struct aml_spdif *p_spdif)
 		mpll_freq = p_spdif->sysclk_freq * 58 / 2; /* 96k */
 #endif
 		clk_set_rate(p_spdif->sysclk, mpll_freq);
-		//clk_set_rate(p_spdif->clk_spdifout,
-		//	p_spdif->sysclk_freq);
-		spdif_set_audio_clk(p_spdif->id,
-				p_spdif->sysclk, p_spdif->sysclk_freq, 0);
+		clk_set_rate(p_spdif->clk_spdifout,
+			p_spdif->sysclk_freq);

 		ret = clk_prepare_enable(p_spdif->sysclk);
 		if (ret) {
@@ -1458,7 +1435,7 @@ static int aml_spdif_parse_of(struct platform_device *pdev)
 	int ret = 0;

 	/* clock for spdif in */
-	if (p_spdif->id == SPDIF_A) {
+	if (p_spdif->id == 0) {
 		/* clock gate */
 		p_spdif->gate_spdifin = devm_clk_get(dev, "gate_spdifin");
 		if (IS_ERR(p_spdif->gate_spdifin)) {
@@ -1592,7 +1569,6 @@ static int aml_spdif_platform_probe(struct platform_device *pdev)
 		dev_warn_once(dev,
 			"check whether to update spdif chipinfo\n");

-	spdif_priv[aml_spdif->id] = aml_spdif;
 	pr_debug("%s, spdif ID = %u\n", __func__, aml_spdif->id);

 	/* get audio controller */
--- a/sound/soc/amlogic/auge/spdif_hw.c
+++ b/sound/soc/amlogic/auge/spdif_hw.c
@@ -420,13 +420,18 @@ static void spdifout_clk_ctrl(int spdif_id, bool is_enable)
 }
 #endif
 static void spdifout_fifo_ctrl(int spdif_id,
-	int fifo_id, int bitwidth, int channels)
+	int fifo_id, int bitwidth, int channels, int lane_i2s)
 {
 	unsigned int frddr_type = spdifout_get_frddr_type(bitwidth);
 	unsigned int offset, reg, i, chmask = 0;
+	unsigned int swap_masks = 0;

-	for (i = 0; i < channels; i++)
-		chmask |= (1 << i);
+	/* spdif always masks two channel */
+	if (lane_i2s * 2 >= channels) {
+		pr_err("invalid lane(%d) and channels(%d)\n",
+				lane_i2s, channels);
+		return;
+	}

 	for (i = 0; i < channels; i++)
 		chmask |= (1 << i);
@@ -445,8 +450,8 @@ static void spdifout_fifo_ctrl(int spdif_id,
 	offset = EE_AUDIO_SPDIFOUT_B_CTRL0 - EE_AUDIO_SPDIFOUT_CTRL0;
 	reg = EE_AUDIO_SPDIFOUT_CTRL0 + offset * spdif_id;
 	audiobus_update_bits(reg,
-		0x3<<21|0x1<<20|0x1<<19|0xff<<4,
-		0x0<<21|0<<20|0<<19|chmask<<4);
+		0x1<<20|0x1<<19|0xff<<4,
+		0<<20|0<<19|chmask<<4);

 	offset = EE_AUDIO_SPDIFOUT_B_CTRL1 - EE_AUDIO_SPDIFOUT_CTRL1;
 	reg = EE_AUDIO_SPDIFOUT_CTRL1 + offset * spdif_id;
@@ -500,7 +505,7 @@ void spdifout_enable(int spdif_id, bool is_enable, bool reenable)
 }

 void spdifout_samesource_set(int spdif_index, int fifo_id,
-	int bitwidth, int channels, bool is_enable)
+	int bitwidth, int channels, bool is_enable, int lane_i2s)
 {
 	int spdif_id;

@@ -510,7 +515,8 @@ void spdifout_samesource_set(int spdif_index, int fifo_id,
 		spdif_id = 0;

 	if (is_enable)
-		spdifout_fifo_ctrl(spdif_id, fifo_id, bitwidth, channels);
+		spdifout_fifo_ctrl(spdif_id,
+			fifo_id, bitwidth, channels, lane_i2s);
 }

 int spdifin_get_sample_rate(void)
@@ -666,7 +672,7 @@ void spdifout_play_with_zerodata(unsigned int spdif_id, bool reenable)

 		/* spdif ctrl */
 		spdifout_fifo_ctrl(spdif_id,
-			frddr_index, bitwidth, runtime.channels);
+			frddr_index, bitwidth, runtime.channels, 0);

 		/* channel status info */
 		spdif_get_channel_status_info(&chsts, sample_rate);
--- a/sound/soc/amlogic/auge/spdif_hw.h
+++ b/sound/soc/amlogic/auge/spdif_hw.h
@@ -78,8 +78,8 @@ extern void aml_spdifout_get_aed_info(int spdifout_id,
 extern void spdifout_to_hdmitx_ctrl(int spdif_index);

 extern void spdifout_samesource_set(int spdif_index, int fifo_id,
-	int bitwidth, int channels, bool is_enable);
-extern void spdifout_enable(int spdif_id, bool is_enable);
+	int bitwidth, int channels, bool is_enable, int lane_i2s);
+extern void spdifout_enable(int spdif_id, bool is_enable, bool reenable);

 extern int spdifin_get_sample_rate(void);

--- a/sound/soc/amlogic/auge/tdm.c
+++ b/sound/soc/amlogic/auge/tdm.c
@@ -120,7 +120,7 @@ static const struct snd_pcm_hardware aml_tdm_hardware = {
 	    SNDRV_PCM_FMTBIT_S32_LE,

 	.period_bytes_min = 64,
-	.period_bytes_max = 256 * 1024 * 2,
+	.period_bytes_max = 256 * 1024,
 	.periods_min = 2,
 	.periods_max = 1024,
 	.buffer_bytes_max = 1024 * 1024,
@@ -131,6 +131,35 @@ static const struct snd_pcm_hardware aml_tdm_hardware = {
 	.channels_max = 32,
 };

+static int tdm_clk_get(struct snd_kcontrol *kcontrol,
+					struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+	struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
+
+	ucontrol->value.enumerated.item[0] = clk_get_rate(p_tdm->mclk);
+	return 0;
+}
+
+static int tdm_clk_set(struct snd_kcontrol *kcontrol,
+					struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+	struct aml_tdm *p_tdm = snd_soc_dai_get_drvdata(cpu_dai);
+
+	int mclk_rate = p_tdm->last_mclk_freq;
+	int value = ucontrol->value.enumerated.item[0];
+
+	if (value > 2000000 || value < 0) {
+		pr_err("Fine tdm clk setting range (0~2000000), %d\n", value);
+		return 0;
+	}
+	mclk_rate += (value - 1000000);
+
+	aml_dai_set_tdm_sysclk(cpu_dai, 0, mclk_rate, 0);
+
+	return 0;
+}

 static int tdmin_clk_get(struct snd_kcontrol *kcontrol,
 			struct snd_ctl_elem_value *ucontrol)
@@ -172,10 +201,16 @@ static const struct soc_enum i2sin_clk_enum[] = {
 static const struct snd_kcontrol_new snd_tdm_controls[] = {
 	SOC_ENUM_EXT("I2SIn CLK", i2sin_clk_enum,
 				tdmin_clk_get,
-				NULL)
+				NULL),
+
+	SOC_SINGLE_EXT("TDM MCLK Fine Setting",
+				0, 0, 2000000, 0,
+				tdm_clk_get,
+				tdm_clk_set),
 };


+
 static irqreturn_t aml_tdm_ddr_isr(int irq, void *devid)
 {
 	struct snd_pcm_substream *substream = (struct snd_pcm_substream *)devid;
@@ -435,8 +470,6 @@ static int aml_dai_tdm_prepare(struct snd_pcm_substream *substream,
 			i2s_to_hdmitx_ctrl(p_tdm->id);
 			aout_notifier_call_chain(AOUT_EVENT_IEC_60958_PCM,
 				substream);
-		} else {
-			i2s_to_hdmitx_disable();
 		}

 		fifo_id = aml_frddr_get_fifo_id(fr);
@@ -580,14 +613,6 @@ static int aml_dai_tdm_trigger(struct snd_pcm_substream *substream, int cmd,

 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 			dev_info(substream->pcm->card->dev, "tdm playback enable\n");
-			/* share buffer trigger */
-			if (p_tdm->chipinfo
-				&& p_tdm->chipinfo->same_src_fn
-				&& (p_tdm->samesource_sel >= 0)
-				&& (aml_check_sharebuffer_valid(p_tdm->fddr,
-						p_tdm->samesource_sel))) {
-				sharebuffer_trigger(cmd, p_tdm->samesource_sel);
-			}
 			aml_frddr_enable(p_tdm->fddr, 1);
 			aml_tdm_enable(p_tdm->actrl,
 				substream->stream, p_tdm->id, true);
@@ -622,9 +647,6 @@ static int aml_dai_tdm_trigger(struct snd_pcm_substream *substream, int cmd,

 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 			dev_info(substream->pcm->card->dev, "tdm playback stop\n");
-			memset(substream->runtime->dma_area,
-				0, substream->runtime->dma_bytes);
-			mdelay(3);
 			aml_frddr_enable(p_tdm->fddr, 0);
 			aml_tdm_mute_playback(p_tdm->actrl, p_tdm->id,
 					true, p_tdm->lane_cnt);