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clk/rockchip: rk3588: Add CLK_SET_RATE_PARENT to dclk_vop2_src

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Allow dclk_vop2_src to change parent rate.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I03d0b39c6b80b6c4e3859449cf66a2f43d8235be
This commit is contained in:
Wyon Bi
2021-11-16 20:28:25 +08:00
committed by Tao Huang
parent 471459e6d7
commit 3a10024049
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3588.c
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@@ -2185,7 +2185,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0,
RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 11, GFLAGS),
COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, 0,
COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 12, GFLAGS),
COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,