media: rockchip: fec: add module parameter cache_linesize

mapping between value and mode:
0: 64B
1: 64B
2: 128B(default)
3: 128B

Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
Change-Id: Ic4bf8ab9486e1fabeedce2b5baeebb8bed6edba8
This commit is contained in:
Xu Hongfei
2025-04-16 11:59:40 +08:00
committed by Tao Huang
parent 14c4d46162
commit 3a1446746c
3 changed files with 17 additions and 4 deletions

View File

@@ -13,10 +13,14 @@ int rkfec_debug;
module_param_named(debug, rkfec_debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level (0-6)");
int rkfec_stdfps = 30;
static int rkfec_stdfps = 30;
module_param_named(standardfps, rkfec_stdfps, int, 0644);
MODULE_PARM_DESC(standardfps, "standard fps");
static int rkfec_cache_linesize = 2;
module_param_named(cache_linesize, rkfec_cache_linesize, int, 0644);
MODULE_PARM_DESC(cache_linesize, "Cache linesize (0-3)");
#if IS_LINUX_VERSION_AT_LEAST_6_1
#define GET_SG_TABLE(mem_ops, off_buf) mem_ops->cookie(&(off_buf)->vb, (off_buf)->mem)
#else
@@ -443,8 +447,10 @@ static int fec_running(struct file *file, struct rkfec_in_out *buf)
writel(0, base + RKFEC_CLK_DIS);
// cache
writel(0x1c, base + RKFEC_CACHE_MAX_READS);
writel(0x27, base + RKFEC_CACHE_CTRL);
val = SW_CACHE_LINESIZE(rkfec_cache_linesize) | 0x7;
writel(val, base + RKFEC_CACHE_CTRL);
//update
writel(SYS_FEC_FORCE_UPD, base + RKFEC_UPD);

View File

@@ -32,8 +32,8 @@ static void offline_fec_show_hw(struct seq_file *p, struct rkfec_hw_dev *hw)
};
static const char * const lut_density[] = {
"16x8",
"32x16",
"16x8",
"4x4"
};
@@ -86,7 +86,7 @@ static int offline_fec_show(struct seq_file *p, void *v)
seq_printf(p, "%-10s Version:v%02x.%02x.%02x\n", ofl->v4l2_dev.name,
RKFEC_DRIVER_VERSION >> 16,
(RKFEC_DRIVER_VERSION & 0xff00) >> 8,
RKFEC_DRIVER_VERSION & 0x00ff);
RKFEC_DRIVER_VERSION & 0xff);
for (i = 0; i < ofl->hw->clks_num; i++) {
seq_printf(p, "%-10s %ld\n", ofl->hw->match_data->clks[i],
clk_get_rate(ofl->hw->clks[i]));

View File

@@ -123,6 +123,13 @@
/* LUT SIZE */
#define SW_LUT_SIZE(x) ((x) & 0x3fffff)
/* FEC_CACHE_CTRL */
#define SW_CACHE_LINESIZE(x) ((x & 0x3) << 4)
#define SW_CACHE_FORCE_BSP(x) ((x & 0x1) << 12)
#define SW_REPLACE_STRATEGY(x) ((x & 0x1) << 9)
#define SW_CACHELINE_EN(x) ((x & 0x1) << 13)
#define SW_CACHE_BYPASS_EN(x) ((x & 0x1) << 6)
/* FEC_INT_EN */
#define PBUF_BD_CRS_P BIT(0)
#define FEC_STOP_IRQ BIT(1)