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mfd: rk630: update pinctrl iomux select

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Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Ifdef9505fc74ed34fb69540a3d52765ad70538e5
This commit is contained in:
Steven Liu
2022-03-09 17:42:40 +08:00
committed by Tao Huang
parent 2ce635afa3
commit 3a33a3c953
2 changed files with 18 additions and 20 deletions
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4
drivers/gpu/drm/bridge/rk630-tve.c
View File

@@ -263,8 +263,8 @@ static int rk630_tve_enable(struct rk630_tve *tve)
/* config bt656 input gpio*/
regmap_write(tve->grf, PLUMAGE_GRF_GPIO0A_IOMUX, 0x55555555);
regmap_update_bits(tve->grf, PLUMAGE_GRF_GPIO0B_IOMUX, GPIO0B0_SEL_MASK,
GPIO0B0_SEL(1));
regmap_update_bits(tve->grf, PLUMAGE_GRF_GPIO0B_IOMUX, PIN0_SEL_MASK,
PIN0_SEL(1));
regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON3, VDAC_ENDAC0_MASK,
VDAC_ENDAC0(0));

34
include/linux/mfd/rk630.h
View File

@@ -63,29 +63,27 @@
#define GRF_REG(x) ((x) + 0x20000)
#define PLUMAGE_GRF_GPIO0A_IOMUX GRF_REG(0x0000)
#define GPIO0A0_SEL_MASK HIWORD_MASK(1, 0)
#define GPIO0A0_SEL(x) HIWORD_UPDATE(x, 1, 0)
#define GPIO0A1_SEL_MASK HIWORD_MASK(3, 2)
#define GPIO0A1_SEL(x) HIWORD_UPDATE(x, 3, 2)
#define GPIO0A2_SEL_MASK HIWORD_MASK(5, 4)
#define GPIO0A2_SEL(x) HIWORD_UPDATE(x, 5, 4)
#define GPIO0A3_SEL_MASK HIWORD_MASK(7, 6)
#define GPIO0A3_SEL(x) HIWORD_UPDATE(x, 7, 6)
#define GPIO0A4_SEL_MASK HIWORD_MASK(9, 8)
#define GPIO0A4_SEL(x) HIWORD_UPDATE(x, 9, 8)
#define GPIO0A5_SEL_MASK HIWORD_MASK(11, 10)
#define GPIO0A5_SEL(x) HIWORD_UPDATE(x, 11, 10)
#define GPIO0A6_SEL_MASK HIWORD_MASK(13, 12)
#define GPIO0A6_SEL(x) HIWORD_UPDATE(x, 13, 12)
#define GPIO0A7_SEL_MASK HIWORD_MASK(15, 14)
#define GPIO0A7_SEL(x) HIWORD_UPDATE(x, 15, 14)
#define PLUMAGE_GRF_GPIO0B_IOMUX GRF_REG(0x0008)
#define GPIO0B0_SEL_MASK HIWORD_MASK(1, 0)
#define GPIO0B0_SEL(x) HIWORD_UPDATE(x, 1, 0)
#define PLUMAGE_GRF_GPIO0C_IOMUX GRF_REG(0x0010)
#define PLUMAGE_GRF_GPIO0D_IOMUX GRF_REG(0x0018)
#define PLUMAGE_GRF_GPIO1A_IOMUX GRF_REG(0x0020)
#define PLUMAGE_GRF_GPIO1B_IOMUX GRF_REG(0x0028)
#define PIN0_SEL_MASK HIWORD_MASK(1, 0)
#define PIN0_SEL(x) HIWORD_UPDATE(x, 1, 0)
#define PIN1_SEL_MASK HIWORD_MASK(3, 2)
#define PIN1_SEL(x) HIWORD_UPDATE(x, 3, 2)
#define PIN2_SEL_MASK HIWORD_MASK(5, 4)
#define PIN2_SEL(x) HIWORD_UPDATE(x, 5, 4)
#define PIN3_SEL_MASK HIWORD_MASK(7, 6)
#define PIN3_SEL(x) HIWORD_UPDATE(x, 7, 6)
#define PIN4_SEL_MASK HIWORD_MASK(9, 8)
#define PIN4_SEL(x) HIWORD_UPDATE(x, 9, 8)
#define PIN5_SEL_MASK HIWORD_MASK(11, 10)
#define PIN5_SEL(x) HIWORD_UPDATE(x, 11, 10)
#define PIN6_SEL_MASK HIWORD_MASK(13, 12)
#define PIN6_SEL(x) HIWORD_UPDATE(x, 13, 12)
#define PIN7_SEL_MASK HIWORD_MASK(15, 14)
#define PIN7_SEL(x) HIWORD_UPDATE(x, 15, 14)
#define PLUMAGE_GRF_GPIO0A_P GRF_REG(0x0080)
#define PLUMAGE_GRF_GPIO0B_P GRF_REG(0x0084)
#define PLUMAGE_GRF_GPIO0C_P GRF_REG(0x0088)