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drm/rockchip: vop2: move crtc_clock check to mode_fixup for rk3528

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Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I207dbe09f17991e9a107cc2df5e7b130600be7b7
This commit is contained in:
Damon Ding
2023-05-10 09:29:33 +08:00
parent 58e55eb624
commit 3aa5acec15
1 changed files with 10 additions and 11 deletions
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21
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -6856,6 +6856,14 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
if (mode->flags & DRM_MODE_FLAG_DBLCLK || vcstate->output_if & VOP_OUTPUT_IF_BT656)
adj_mode->crtc_clock *= 2;
/*
* For RK3528, the path of CVBS output is like:
* VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC
* The vop2 dclk should be four times crtc_clock for CVBS sampling clock needs.
*/
if (vop2->version == VOP_VERSION_RK3528 && vcstate->output_if & VOP_OUTPUT_IF_BT656)
adj_mode->crtc_clock *= 4;
if (vp->mcu_timing.mcu_pix_total)
adj_mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(vcstate->bus_format) *
(vp->mcu_timing.mcu_pix_total + 1);
@@ -8111,17 +8119,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
DRM_DEV_INFO(vop2->dev, "set %s to %ld, get %ld\n",
__clk_get_name(vp->dclk), dclk->rate, clk_get_rate(vp->dclk));
} else {
/*
* For RK3528, the path of CVBS output is like:
* VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC
* The vop2 dclk should be four times crtc_clock for CVBS sampling clock needs.
*/
if (vop2->version == VOP_VERSION_RK3528 && vcstate->output_if & VOP_OUTPUT_IF_BT656)
rockchip_drm_dclk_set_rate(vop2->version, vp->dclk,
4 * adjusted_mode->crtc_clock * 1000);
else
rockchip_drm_dclk_set_rate(vop2->version, vp->dclk,
adjusted_mode->crtc_clock * 1000);
rockchip_drm_dclk_set_rate(vop2->version, vp->dclk,
adjusted_mode->crtc_clock * 1000);
}
if (vp_data->feature & VOP_FEATURE_OVERSCAN)