mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-05 18:41:58 +09:00
Merge tag 'v5.19' into android-mainline
Linux 5.19 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I87af07e721283537e21d52f18639a393dcedace0
This commit is contained in:
@@ -3184,6 +3184,7 @@
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no_entry_flush [PPC]
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no_uaccess_flush [PPC]
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mmio_stale_data=off [X86]
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retbleed=off [X86]
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Exceptions:
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This does not have any effect on
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@@ -3206,6 +3207,7 @@
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mds=full,nosmt [X86]
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tsx_async_abort=full,nosmt [X86]
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mmio_stale_data=full,nosmt [X86]
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retbleed=auto,nosmt [X86]
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mminit_loglevel=
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[KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this
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2
Makefile
2
Makefile
@@ -2,7 +2,7 @@
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VERSION = 5
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PATCHLEVEL = 19
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SUBLEVEL = 0
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EXTRAVERSION = -rc8
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EXTRAVERSION =
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NAME = Superb Owl
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# *DOCUMENTATION*
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@@ -72,7 +72,6 @@ static inline u64 lower_bits(u64 val, unsigned int bits)
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struct real_mode_header;
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enum stack_type;
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struct ghcb;
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/* Early IDT entry points for #VC handler */
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extern void vc_no_ghcb(void);
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@@ -156,11 +155,7 @@ static __always_inline void sev_es_nmi_complete(void)
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__sev_es_nmi_complete();
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}
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extern int __init sev_es_efi_map_ghcbs(pgd_t *pgd);
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extern enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb,
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bool set_ghcb_msr,
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struct es_em_ctxt *ctxt,
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u64 exit_code, u64 exit_info_1,
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u64 exit_info_2);
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static inline int rmpadjust(unsigned long vaddr, bool rmp_psize, unsigned long attrs)
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{
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int rc;
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@@ -1520,6 +1520,7 @@ static void __init spectre_v2_select_mitigation(void)
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* enable IBRS around firmware calls.
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*/
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if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
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boot_cpu_has(X86_FEATURE_IBPB) &&
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(boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
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boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) {
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@@ -219,9 +219,10 @@ static enum es_result verify_exception_info(struct ghcb *ghcb, struct es_em_ctxt
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return ES_VMM_ERROR;
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}
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enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, bool set_ghcb_msr,
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struct es_em_ctxt *ctxt, u64 exit_code,
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u64 exit_info_1, u64 exit_info_2)
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static enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb,
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struct es_em_ctxt *ctxt,
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u64 exit_code, u64 exit_info_1,
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u64 exit_info_2)
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{
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/* Fill in protocol and format specifiers */
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ghcb->protocol_version = ghcb_version;
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@@ -231,14 +232,7 @@ enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, bool set_ghcb_msr,
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ghcb_set_sw_exit_info_1(ghcb, exit_info_1);
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ghcb_set_sw_exit_info_2(ghcb, exit_info_2);
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/*
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* Hyper-V unenlightened guests use a paravisor for communicating and
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* GHCB pages are being allocated and set up by that paravisor. Linux
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* should not change the GHCB page's physical address.
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*/
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if (set_ghcb_msr)
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sev_es_wr_ghcb_msr(__pa(ghcb));
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sev_es_wr_ghcb_msr(__pa(ghcb));
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VMGEXIT();
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return verify_exception_info(ghcb, ctxt);
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@@ -795,7 +789,7 @@ static enum es_result vc_handle_ioio(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
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*/
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sw_scratch = __pa(ghcb) + offsetof(struct ghcb, shared_buffer);
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ghcb_set_sw_scratch(ghcb, sw_scratch);
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ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_IOIO,
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ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_IOIO,
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exit_info_1, exit_info_2);
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if (ret != ES_OK)
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return ret;
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@@ -837,8 +831,7 @@ static enum es_result vc_handle_ioio(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
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ghcb_set_rax(ghcb, rax);
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ret = sev_es_ghcb_hv_call(ghcb, true, ctxt,
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SVM_EXIT_IOIO, exit_info_1, 0);
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ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_IOIO, exit_info_1, 0);
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if (ret != ES_OK)
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return ret;
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@@ -894,7 +887,7 @@ static enum es_result vc_handle_cpuid(struct ghcb *ghcb,
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/* xgetbv will cause #GP - use reset value for xcr0 */
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ghcb_set_xcr0(ghcb, 1);
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ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_CPUID, 0, 0);
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ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_CPUID, 0, 0);
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if (ret != ES_OK)
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return ret;
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@@ -919,7 +912,7 @@ static enum es_result vc_handle_rdtsc(struct ghcb *ghcb,
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bool rdtscp = (exit_code == SVM_EXIT_RDTSCP);
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enum es_result ret;
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ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, exit_code, 0, 0);
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ret = sev_es_ghcb_hv_call(ghcb, ctxt, exit_code, 0, 0);
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if (ret != ES_OK)
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return ret;
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@@ -786,7 +786,7 @@ static int vmgexit_psc(struct snp_psc_desc *desc)
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ghcb_set_sw_scratch(ghcb, (u64)__pa(data));
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/* This will advance the shared buffer data points to. */
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ret = sev_es_ghcb_hv_call(ghcb, true, &ctxt, SVM_VMGEXIT_PSC, 0, 0);
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ret = sev_es_ghcb_hv_call(ghcb, &ctxt, SVM_VMGEXIT_PSC, 0, 0);
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/*
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* Page State Change VMGEXIT can pass error code through
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@@ -1212,8 +1212,7 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
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ghcb_set_rdx(ghcb, regs->dx);
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}
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ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_MSR,
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exit_info_1, 0);
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ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_MSR, exit_info_1, 0);
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if ((ret == ES_OK) && (!exit_info_1)) {
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regs->ax = ghcb->save.rax;
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@@ -1452,7 +1451,7 @@ static enum es_result vc_do_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
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ghcb_set_sw_scratch(ghcb, ghcb_pa + offsetof(struct ghcb, shared_buffer));
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return sev_es_ghcb_hv_call(ghcb, true, ctxt, exit_code, exit_info_1, exit_info_2);
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return sev_es_ghcb_hv_call(ghcb, ctxt, exit_code, exit_info_1, exit_info_2);
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}
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/*
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@@ -1628,7 +1627,7 @@ static enum es_result vc_handle_dr7_write(struct ghcb *ghcb,
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/* Using a value of 0 for ExitInfo1 means RAX holds the value */
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ghcb_set_rax(ghcb, val);
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ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_WRITE_DR7, 0, 0);
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ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_WRITE_DR7, 0, 0);
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if (ret != ES_OK)
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return ret;
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@@ -1658,7 +1657,7 @@ static enum es_result vc_handle_dr7_read(struct ghcb *ghcb,
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static enum es_result vc_handle_wbinvd(struct ghcb *ghcb,
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struct es_em_ctxt *ctxt)
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{
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return sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_WBINVD, 0, 0);
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return sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_WBINVD, 0, 0);
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}
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static enum es_result vc_handle_rdpmc(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
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@@ -1667,7 +1666,7 @@ static enum es_result vc_handle_rdpmc(struct ghcb *ghcb, struct es_em_ctxt *ctxt
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ghcb_set_rcx(ghcb, ctxt->regs->cx);
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ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_RDPMC, 0, 0);
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ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_RDPMC, 0, 0);
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if (ret != ES_OK)
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return ret;
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@@ -1708,7 +1707,7 @@ static enum es_result vc_handle_vmmcall(struct ghcb *ghcb,
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if (x86_platform.hyper.sev_es_hcall_prepare)
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x86_platform.hyper.sev_es_hcall_prepare(ghcb, ctxt->regs);
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ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_VMMCALL, 0, 0);
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ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_VMMCALL, 0, 0);
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if (ret != ES_OK)
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return ret;
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@@ -2197,7 +2196,7 @@ int snp_issue_guest_request(u64 exit_code, struct snp_req_data *input, unsigned
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ghcb_set_rbx(ghcb, input->data_npages);
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}
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ret = sev_es_ghcb_hv_call(ghcb, true, &ctxt, exit_code, input->req_gpa, input->resp_gpa);
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ret = sev_es_ghcb_hv_call(ghcb, &ctxt, exit_code, input->req_gpa, input->resp_gpa);
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if (ret)
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goto e_put;
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@@ -138,6 +138,7 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
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&r_apb2_rsb_clk.common,
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&r_apb1_ir_clk.common,
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&r_apb1_w1_clk.common,
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&r_apb1_rtc_clk.common,
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&ir_clk.common,
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&w1_clk.common,
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};
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@@ -103,9 +103,14 @@ static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
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dmi_memdev_name(handle, &bank, &device);
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/* both strings must be non-zero */
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if (bank && *bank && device && *device)
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snprintf(dimm->label, sizeof(dimm->label), "%s %s", bank, device);
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/*
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* Set to a NULL string when both bank and device are zero. In this case,
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* the label assigned by default will be preserved.
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*/
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snprintf(dimm->label, sizeof(dimm->label), "%s%s%s",
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(bank && *bank) ? bank : "",
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(bank && *bank && device && *device) ? " " : "",
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(device && *device) ? device : "");
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}
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static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)
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@@ -514,6 +514,28 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
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memset(p, 0, sizeof(*p));
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}
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static void enable_intr(struct synps_edac_priv *priv)
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{
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/* Enable UE/CE Interrupts */
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if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
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writel(DDR_UE_MASK | DDR_CE_MASK,
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priv->baseaddr + ECC_CLR_OFST);
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else
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writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
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priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
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}
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static void disable_intr(struct synps_edac_priv *priv)
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{
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/* Disable UE/CE Interrupts */
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if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
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writel(0x0, priv->baseaddr + ECC_CLR_OFST);
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else
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writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
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priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
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}
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/**
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* intr_handler - Interrupt Handler for ECC interrupts.
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* @irq: IRQ number.
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@@ -555,6 +577,9 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
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/* v3.0 of the controller does not have this register */
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if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
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writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
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else
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enable_intr(priv);
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return IRQ_HANDLED;
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}
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@@ -837,25 +862,6 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
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init_csrows(mci);
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}
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static void enable_intr(struct synps_edac_priv *priv)
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{
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/* Enable UE/CE Interrupts */
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if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
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writel(DDR_UE_MASK | DDR_CE_MASK,
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priv->baseaddr + ECC_CLR_OFST);
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else
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writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
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priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
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}
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static void disable_intr(struct synps_edac_priv *priv)
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{
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/* Disable UE/CE Interrupts */
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writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
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priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
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}
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static int setup_irq(struct mem_ctl_info *mci,
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struct platform_device *pdev)
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{
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@@ -7,12 +7,11 @@ CONFIG_DEBUG_SLAB=y
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CONFIG_DEBUG_KMEMLEAK=y
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CONFIG_DEBUG_PAGEALLOC=y
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CONFIG_SLUB_DEBUG_ON=y
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CONFIG_KMEMCHECK=y
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CONFIG_DEBUG_OBJECTS=y
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CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
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CONFIG_GCOV_KERNEL=y
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CONFIG_LOCKDEP=y
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CONFIG_PROVE_LOCKING=y
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CONFIG_SCHEDSTATS=y
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CONFIG_VMLINUX_VALIDATION=y
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CONFIG_NOINSTR_VALIDATION=y
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CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
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@@ -335,8 +335,6 @@ struct rwsem_waiter {
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struct task_struct *task;
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enum rwsem_waiter_type type;
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unsigned long timeout;
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/* Writer only, not initialized in reader */
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bool handoff_set;
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};
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#define rwsem_first_waiter(sem) \
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@@ -459,10 +457,12 @@ static void rwsem_mark_wake(struct rw_semaphore *sem,
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* to give up the lock), request a HANDOFF to
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* force the issue.
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*/
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if (!(oldcount & RWSEM_FLAG_HANDOFF) &&
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time_after(jiffies, waiter->timeout)) {
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adjustment -= RWSEM_FLAG_HANDOFF;
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lockevent_inc(rwsem_rlock_handoff);
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if (time_after(jiffies, waiter->timeout)) {
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if (!(oldcount & RWSEM_FLAG_HANDOFF)) {
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adjustment -= RWSEM_FLAG_HANDOFF;
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lockevent_inc(rwsem_rlock_handoff);
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}
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waiter->handoff_set = true;
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}
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atomic_long_add(-adjustment, &sem->count);
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@@ -599,7 +599,7 @@ rwsem_del_wake_waiter(struct rw_semaphore *sem, struct rwsem_waiter *waiter,
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static inline bool rwsem_try_write_lock(struct rw_semaphore *sem,
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struct rwsem_waiter *waiter)
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{
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bool first = rwsem_first_waiter(sem) == waiter;
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struct rwsem_waiter *first = rwsem_first_waiter(sem);
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long count, new;
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lockdep_assert_held(&sem->wait_lock);
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@@ -609,11 +609,20 @@ static inline bool rwsem_try_write_lock(struct rw_semaphore *sem,
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bool has_handoff = !!(count & RWSEM_FLAG_HANDOFF);
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if (has_handoff) {
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if (!first)
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/*
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* Honor handoff bit and yield only when the first
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* waiter is the one that set it. Otherwisee, we
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* still try to acquire the rwsem.
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*/
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if (first->handoff_set && (waiter != first))
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return false;
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/* First waiter inherits a previously set handoff bit */
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waiter->handoff_set = true;
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/*
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* First waiter can inherit a previously set handoff
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* bit and spin on rwsem if lock acquisition fails.
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*/
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if (waiter == first)
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waiter->handoff_set = true;
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}
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new = count;
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@@ -1027,6 +1036,7 @@ queue:
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waiter.task = current;
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waiter.type = RWSEM_WAITING_FOR_READ;
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waiter.timeout = jiffies + RWSEM_WAIT_TIMEOUT;
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waiter.handoff_set = false;
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raw_spin_lock_irq(&sem->wait_lock);
|
||||
if (list_empty(&sem->wait_list)) {
|
||||
|
||||
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