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media: rockchip: isp: dmatx support embedded and shield pixels data

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Change-Id: Ifb07d7a7b11d44a5843dfe3a66284e38b98fbbb6
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2021-05-10 16:58:13 +08:00
committed by Tao Huang
parent 7b82a42749
commit 3b4cc8c2d3
7 changed files with 94 additions and 13 deletions
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21
drivers/media/platform/rockchip/isp/capture_v20.c
View File

@@ -116,6 +116,16 @@ static const struct capture_fmt dmatx_fmts[] = {
.fmt_type = FMT_YUV,
.bpp = { 16 },
.mplanes = 1,
}, {
.fourcc = V4l2_PIX_FMT_EBD8,
.fmt_type = FMT_EBD,
.bpp = { 8 },
.mplanes = 1,
}, {
.fourcc = V4l2_PIX_FMT_SPD16,
.fmt_type = FMT_SPD,
.bpp = { 16 },
.mplanes = 1,
}
};
@@ -2195,6 +2205,9 @@ void rkisp_mi_v20_isr(u32 mis_val, struct rkisp_device *dev)
end_tx1 = true;
if (i == RKISP_STREAM_DMATX2)
end_tx2 = true;
/* DMATX3 no csi frame end isr, mi isr instead */
if (i == RKISP_STREAM_DMATX3)
atomic_inc(&stream->sequence);
mi_frame_end_int_clear(stream);
@@ -2240,6 +2253,10 @@ void rkisp_mipi_v20_isr(unsigned int phy, unsigned int packet,
{
struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
struct rkisp_stream *stream;
u32 packet_err = PACKET_ERR_F_BNDRY_MATCG | PACKET_ERR_F_SEQ |
PACKET_ERR_FRAME_DATA | PACKET_ERR_ECC_1BIT |
PACKET_ERR_ECC_2BIT | PACKET_ERR_CHECKSUM;
u32 state_err = RAW_WR_SIZE_ERR | RAW_RD_SIZE_ERR;
int i;
v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
@@ -2248,7 +2265,7 @@ void rkisp_mipi_v20_isr(unsigned int phy, unsigned int packet,
if (phy && (dev->isp_inp & INP_CSI) &&
dev->csi_dev.err_cnt++ < RKISP_CONTI_ERR_MAX)
v4l2_warn(v4l2_dev, "MIPI error: phy: 0x%08x\n", phy);
if (packet && (dev->isp_inp & INP_CSI) &&
if ((packet & packet_err) && (dev->isp_inp & INP_CSI) &&
dev->csi_dev.err_cnt < RKISP_CONTI_ERR_MAX) {
if (packet & 0xfff)
dev->csi_dev.err_cnt++;
@@ -2257,7 +2274,7 @@ void rkisp_mipi_v20_isr(unsigned int phy, unsigned int packet,
if (overflow &&
dev->csi_dev.err_cnt++ < RKISP_CONTI_ERR_MAX)
v4l2_warn(v4l2_dev, "MIPI error: overflow: 0x%08x\n", overflow);
if (state & 0xeff00)
if (state & state_err)
v4l2_warn(v4l2_dev, "MIPI error: size: 0x%08x\n", state);
if (state & MIPI_DROP_FRM)
v4l2_warn(v4l2_dev, "MIPI drop frame\n");

8
drivers/media/platform/rockchip/isp/capture_v21.c
View File

@@ -1472,6 +1472,10 @@ void rkisp_mipi_v21_isr(unsigned int phy, unsigned int packet,
{
struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
struct rkisp_stream *stream;
u32 packet_err = PACKET_ERR_F_BNDRY_MATCG | PACKET_ERR_F_SEQ |
PACKET_ERR_FRAME_DATA | PACKET_ERR_ECC_1BIT |
PACKET_ERR_ECC_2BIT | PACKET_ERR_CHECKSUM;
u32 state_err = RAW_WR_SIZE_ERR | RAW_RD_SIZE_ERR;
int i, id;
v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
@@ -1480,7 +1484,7 @@ void rkisp_mipi_v21_isr(unsigned int phy, unsigned int packet,
if (phy && (dev->isp_inp & INP_CSI) &&
dev->csi_dev.err_cnt++ < RKISP_CONTI_ERR_MAX)
v4l2_warn(v4l2_dev, "MIPI error: phy: 0x%08x\n", phy);
if (packet && (dev->isp_inp & INP_CSI) &&
if ((packet & packet_err) && (dev->isp_inp & INP_CSI) &&
dev->csi_dev.err_cnt < RKISP_CONTI_ERR_MAX) {
if (packet & 0xfff)
dev->csi_dev.err_cnt++;
@@ -1488,7 +1492,7 @@ void rkisp_mipi_v21_isr(unsigned int phy, unsigned int packet,
}
if (overflow && dev->csi_dev.err_cnt++ < RKISP_CONTI_ERR_MAX)
v4l2_warn(v4l2_dev, "MIPI error: overflow: 0x%08x\n", overflow);
if (state & 0xeff00)
if (state & state_err)
v4l2_warn(v4l2_dev, "MIPI error: size: 0x%08x\n", state);
if (state & ISP21_MIPI_DROP_FRM)
v4l2_warn(v4l2_dev, "MIPI drop frame\n");

2
drivers/media/platform/rockchip/isp/common.h
View File

@@ -100,6 +100,8 @@ enum rkisp_fmt_pix_type {
FMT_BAYER,
FMT_JPEG,
FMT_FBCGAIN,
FMT_EBD,
FMT_SPD,
FMT_MAX
};

32
drivers/media/platform/rockchip/isp/csi.c
View File

@@ -320,10 +320,24 @@ static int csi_config(struct rkisp_csi_device *csi)
/* clear interrupts state */
rkisp_read(dev, CSI2RX_ERR_PHY, true);
/* set interrupts mask */
rkisp_write(dev, CSI2RX_MASK_PHY, 0xF0FFFF, true);
rkisp_write(dev, CSI2RX_MASK_PACKET, 0xF1FFFFF, true);
rkisp_write(dev, CSI2RX_MASK_OVERFLOW, 0x7F7FF1, true);
rkisp_write(dev, CSI2RX_MASK_STAT, 0x7FFFFF0F, true);
val = PHY_ERR_SOTHS | PHY_ERR_SOTSYNCHS |
PHY_ERR_EOTSYNCHS | PHY_ERR_ESC | PHY_ERR_CTL;
rkisp_write(dev, CSI2RX_MASK_PHY, val, true);
val = PACKET_ERR_F_BNDRY_MATCG | PACKET_ERR_F_SEQ |
PACKET_ERR_FRAME_DATA | PACKET_ERR_ECC_1BIT |
PACKET_ERR_ECC_2BIT | PACKET_ERR_CHECKSUM;
rkisp_write(dev, CSI2RX_MASK_PACKET, val, true);
val = AFIFO0_OVERFLOW | AFIFO1X_OVERFLOW |
LAFIFO1X_OVERFLOW | AFIFO2X_OVERFLOW |
IBUFX3_OVERFLOW | IBUF3R_OVERFLOW |
Y_STAT_AFIFOX3_OVERFLOW;
rkisp_write(dev, CSI2RX_MASK_OVERFLOW, val, true);
val = RAW0_WR_FRAME | RAW1_WR_FRAME | RAW2_WR_FRAME |
MIPI_DROP_FRM | RAW_WR_SIZE_ERR | MIPI_LINECNT |
RAW_RD_SIZE_ERR | MIPI_FRAME_ST_VC(0xf) |
MIPI_FRAME_END_VC(0xf) | RAW0_Y_STATE |
RAW1_Y_STATE | RAW2_Y_STATE;
rkisp_write(dev, CSI2RX_MASK_STAT, val, true);
/* hdr merge */
switch (dev->hdr.op_mode) {
@@ -465,13 +479,13 @@ int rkisp_csi_config_patch(struct rkisp_device *dev)
}
}
rkisp_write(dev, ISP_HDRMGE_BASE, val, false);
rkisp_set_bits(dev, CSI2RX_MASK_STAT, 0, RAW_RD_SIZE_ERR, true);
}
if (IS_HDR_RDBK(dev->hdr.op_mode)) {
rkisp_write(dev, CSI2RX_MASK_STAT, 0x700FFF0F, true);
rkisp_set_bits(dev, CTRL_SWS_CFG,
0, SW_MPIP_DROP_FRM_DIS, true);
}
if (IS_HDR_RDBK(dev->hdr.op_mode))
rkisp_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, true);
memset(dev->csi_dev.filt_state, 0, sizeof(dev->csi_dev.filt_state));
dev->csi_dev.frame_cnt = -1;
dev->csi_dev.frame_cnt_x1 = -1;

2
drivers/media/platform/rockchip/isp/regs.h
View File

@@ -392,6 +392,7 @@
#define CIF_MIPI_DATA_SEL_VC(a) (((a) & 0x3) << 6)
#define CIF_MIPI_DATA_SEL_DT(a) (((a) & 0x3F) << 0)
/* MIPI DATA_TYPE */
#define CIF_CSI2_DT_EBD 0x12
#define CIF_CSI2_DT_YUV420_8b 0x18
#define CIF_CSI2_DT_YUV420_10b 0x19
#define CIF_CSI2_DT_YUV422_8b 0x1E
@@ -402,6 +403,7 @@
#define CIF_CSI2_DT_RAW8 0x2A
#define CIF_CSI2_DT_RAW10 0x2B
#define CIF_CSI2_DT_RAW12 0x2C
#define CIF_CSI2_DT_SPD 0x2F
/* MIPI_IMSC, MIPI_RIS, MIPI_MIS, MIPI_ICR, MIPI_ISR */
#define CIF_MIPI_SYNC_FIFO_OVFLW(a) (((a) & 0xF) << 0)

30
drivers/media/platform/rockchip/isp/regs_v2x.h
View File

@@ -2362,6 +2362,28 @@
#define SW_CSI_ID6(a) (((a) & 0xff) << 16)
#define SW_CSI_ID7(a) (((a) & 0xff) << 24)
#define PHY_ERR_SOTHS GENMASK(3, 0)
#define PHY_ERR_SOTSYNCHS GENMASK(7, 4)
#define PHY_ERR_EOTSYNCHS GENMASK(11, 8)
#define PHY_ERR_ESC GENMASK(15, 12)
#define PHY_ERR_CTL GENMASK(23, 20)
#define PACKET_ERR_F_BNDRY_MATCG GENMASK(3, 0)
#define PACKET_ERR_F_SEQ GENMASK(7, 4)
#define PACKET_ERR_FRAME_DATA GENMASK(11, 8)
#define PACKET_ERR_ID GENMASK(15, 12)
#define PACKET_ERR_ECC_1BIT GENMASK(19, 16)
#define PACKET_ERR_ECC_2BIT BIT(20)
#define PACKET_ERR_CHECKSUM GENMASK(27, 24)
#define AFIFO0_OVERFLOW BIT(0)
#define AFIFO1X_OVERFLOW GENMASK(7, 4)
#define LAFIFO1X_OVERFLOW GENMASK(11, 8)
#define AFIFO2X_OVERFLOW GENMASK(14, 12)
#define IBUFX3_OVERFLOW GENMASK(18, 16)
#define IBUF3R_OVERFLOW BIT(19)
#define Y_STAT_AFIFOX3_OVERFLOW GENMASK(22, 20)
#define RAW0_WR_FRAME BIT(0)
#define RAW1_WR_FRAME BIT(1)
#define RAW2_WR_FRAME BIT(2)
@@ -2369,6 +2391,11 @@
#define RAW0_RD_FRAME BIT(4)
#define RAW1_RD_FRAME BIT(5)
#define RAW2_RD_FRAME BIT(6)
#define RAW_WR_SIZE_ERR GENMASK(15, 8)
#define MIPI_LINECNT BIT(16)
#define RAW_RD_SIZE_ERR GENMASK(19, 17)
#define MIPI_FRAME_ST_VC(a) (((a) & 0xf) << 20)
#define MIPI_FRAME_END_VC(a) (((a) & 0xf) << 24)
#define RAW0_Y_STATE BIT(28)
#define RAW1_Y_STATE BIT(29)
#define RAW2_Y_STATE BIT(30)
@@ -2599,6 +2626,9 @@ static inline void raw_wr_set_pic_size(struct rkisp_stream *stream,
if (stream->out_isp_fmt.fmt_type == FMT_YUV)
width *= 2;
/* hardware received 16bit embedded data */
else if (stream->out_isp_fmt.fmt_type == FMT_EBD)
width /= 2;
writel(height << 16 | width,
base + stream->config->dma.pic_size);
}

12
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -124,6 +124,12 @@ static int mbus_pixelcode_to_mipi_dt(u32 pixelcode)
case MEDIA_BUS_FMT_VYUY8_2X8:
mipi_dt = CIF_CSI2_DT_YUV422_8b;
break;
case MEDIA_BUS_FMT_EBD_1X8:
mipi_dt = CIF_CSI2_DT_EBD;
break;
case MEDIA_BUS_FMT_SPD_2X8:
mipi_dt = CIF_CSI2_DT_SPD;
break;
default:
mipi_dt = -EINVAL;
}
@@ -450,6 +456,12 @@ u32 rkisp_mbus_pixelcode_to_v4l2(u32 pixelcode)
case MEDIA_BUS_FMT_SRGGB12_1X12:
pixelformat = V4L2_PIX_FMT_SRGGB12;
break;
case MEDIA_BUS_FMT_EBD_1X8:
pixelformat = V4l2_PIX_FMT_EBD8;
break;
case MEDIA_BUS_FMT_SPD_2X8:
pixelformat = V4l2_PIX_FMT_SPD16;
break;
default:
pixelformat = V4L2_PIX_FMT_SRGGB10;
}