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clk: rockchip: fix rk3288 pll settings

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dkl
2014-03-18 14:27:54 +08:00
parent 0086569bc0
commit 3be9e06dbc
2 changed files with 3 additions and 1 deletions
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2
arch/arm/boot/dts/rk3288.dtsi
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@@ -287,7 +287,7 @@
<&clk_i2s_pll &clk_cpll>;
rockchip,clocks-init-rate =
<&clk_core 792000000>, <&clk_gpll 594000000>,
<&clk_cpll 393216000>, <&clk_npll 500000000>,
<&clk_cpll 384000000>, <&clk_npll 500000000>,
<&aclk_bus_src 300000000>, <&aclk_bus 300000000>,
<&hclk_bus 150000000>, <&pclk_bus 75000000>,
<&clk_crypto 150000000>, <&aclk_peri 300000000>,

2
drivers/clk/rockchip/clk-pll.c
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@@ -11,7 +11,9 @@ static const struct pll_clk_set pll_com_table[] = {
_RK3188_PLL_SET_CLKS(891000, 8, 594, 2),
_RK3188_PLL_SET_CLKS(768000, 1, 64, 2),
_RK3188_PLL_SET_CLKS(594000, 2, 198, 4),
_RK3188_PLL_SET_CLKS(500000, 3, 250, 4),
_RK3188_PLL_SET_CLKS(408000, 1, 68, 4),
_RK3188_PLL_SET_CLKS(396000, 1, 66, 4),
_RK3188_PLL_SET_CLKS(384000, 2, 128, 4),
_RK3188_PLL_SET_CLKS(360000, 1, 60, 4),
_RK3188_PLL_SET_CLKS(300000, 1, 50, 4),