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modify lcd freq

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This commit is contained in:
zyw
2010-12-10 16:31:04 +08:00
parent 5802aa2180
commit 3d128b1bc7
12 changed files with 73 additions and 24 deletions
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3
drivers/video/display/screen/lcd_a060se02.c Normal file → Executable file
View File

@@ -9,6 +9,8 @@
#define OUT_TYPE SCREEN_MCU
#define OUT_FACE OUT_P16BPP4
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 1
#define H_BP 1
@@ -133,6 +135,7 @@ void set_lcd_info(struct rk29fb_screen *screen)
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;

4
drivers/video/display/screen/lcd_hl070vm4.c
View File

@@ -9,7 +9,8 @@
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 27
#define OUT_CLK 27000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
@@ -65,6 +66,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk2918lcd_info *lcd_info
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;

8
drivers/video/display/screen/lcd_hsd100pxn.c Executable file → Normal file
View File

@@ -9,9 +9,9 @@
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 65
#define LCDC_ACLK 150 //29 lcdc axi DMA Ƶ<><C6B5>
#define OUT_FACE OUT_D888_P666
#define OUT_CLK 65000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
@@ -45,6 +45,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
@@ -58,7 +59,6 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->pin_vsync = 0;
screen->pin_den = 0;
screen->pin_dclk = DCLK_POL;
screen->lcdc_aclk = LCDC_ACLK;
/* Swap rule */
screen->swap_rb = SWAP_RB;

4
drivers/video/display/screen/lcd_hsd800x480.c
View File

@@ -11,7 +11,8 @@
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 28
#define OUT_CLK 28000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 1
@@ -66,6 +67,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;

4
drivers/video/display/screen/lcd_hx8357.c
View File

@@ -10,7 +10,8 @@
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P666 /*OUT_P888*/
#define OUT_CLK 10 //***27
#define OUT_CLK 10000000 //***27
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 8
@@ -179,6 +180,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP; /*>2*/
screen->right_margin = H_FP; /*>2*/

4
drivers/video/display/screen/lcd_nt35580.c
View File

@@ -10,7 +10,8 @@
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 24
#define OUT_CLK 24000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 1
@@ -439,6 +440,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk2918lcd_info *lcd_info
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;

3
drivers/video/display/screen/lcd_nt35582.c
View File

@@ -23,6 +23,8 @@
#define LCD_WIDTH 480 //need modify
#define LCD_HEIGHT 800
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
#define P_WR 27
#define USE_FMARK 0 //2 //<2F>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9>FMK (0:<3A><>֧<EFBFBD><D6A7> 1:<3A><><EFBFBD><EFBFBD>֧<EFBFBD><D6A7> 2:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֧<EFBFBD><D6A7>)
#define FRMRATE 60 //MCU<43><55><EFBFBD><EFBFBD>ˢ<EFBFBD><CBA2><EFBFBD><EFBFBD> (FMK<4D><4B>Чʱ<D0A7><CAB1>)
@@ -395,6 +397,7 @@ void set_lcd_info(struct rk29fb_screen *screen)
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;

2
drivers/video/display/screen/lcd_s1d13521.c
View File

@@ -11,6 +11,7 @@
/* Base */
#define OUT_TYPE SCREEN_MCU
#define OUT_FACE OUT_P16BPP4
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 1
@@ -321,6 +322,7 @@ void set_lcd_info(struct rk28fb_screen *screen)
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;
screen->hsync_len = H_PW;

4
drivers/video/display/screen/lcd_td043mgea1.c
View File

@@ -10,7 +10,8 @@
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 27
#define OUT_CLK 27000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 10
@@ -65,6 +66,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;

4
drivers/video/display/screen/lcd_tj048nc01ca.c
View File

@@ -10,7 +10,8 @@
/* Base */
#define OUT_TYPE SCREEN_RGB
#define OUT_FACE OUT_P888
#define OUT_CLK 23
#define OUT_CLK 23000000
#define LCDC_ACLK 150000000 //29 lcdc axi DMA Ƶ<><C6B5>
/* Timing */
#define H_PW 1
@@ -64,6 +65,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
screen->height = LCD_HEIGHT;
/* Timing */
screen->lcdc_aclk = LCDC_ACLK;
screen->pixclock = OUT_CLK;
screen->left_margin = H_BP;
screen->right_margin = H_FP;

50
drivers/video/rk29_fb.c
View File

@@ -401,7 +401,6 @@ int init_lcdc(struct fb_info *info)
LcdMskReg(inf, WIN0_COLOR_KEY_CTRL, m_COLORKEY_EN, v_COLORKEY_EN(0));
LcdMskReg(inf, WIN1_COLOR_KEY_CTRL, m_COLORKEY_EN, v_COLORKEY_EN(0));
LcdWrReg(inf, DSP_CTRL0, 0);
LcdWrReg(inf, DSP_CTRL1, 0);
// initialize all interrupt
@@ -422,15 +421,17 @@ void load_screen(struct fb_info *info, bool initscreen)
int ret = -EINVAL;
struct rk29fb_inf *inf = dev_get_drvdata(info->device);
struct rk29fb_screen *screen = inf->cur_screen;
u16 face = screen->face;
u16 face;
u16 mcu_total, mcu_rwstart, mcu_csstart, mcu_rwend, mcu_csend;
u16 right_margin = screen->right_margin, lower_margin = screen->lower_margin;
u16 x_res = screen->x_res, y_res = screen->y_res;
u32 clk_rate = 0;
u32 dclk_rate = 0;
u32 aclk_rate = 150000000;
if(!g_pdev) return -1;
if(!g_pdev){
printk(">>>>>> %s : %s no g_pdev\n", __FILE__, __FUNCTION__);
return;
}
fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__);
@@ -458,6 +459,33 @@ void load_screen(struct fb_info *info, bool initscreen)
);
// set synchronous pin polarity and data pin swap rule
switch (screen->face)
{
case OUT_P565:
face = OUT_P565;
LcdMskReg(inf, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0));
break;
case OUT_P666:
face = OUT_P666;
LcdMskReg(inf, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1));
break;
case OUT_D888_P565:
face = OUT_P888;
LcdMskReg(inf, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0));
break;
case OUT_D888_P666:
face = OUT_P888;
LcdMskReg(inf, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1));
break;
case OUT_P888:
face = OUT_P888;
LcdMskReg(inf, DSP_CTRL0, m_DITHER_UP_EN, v_DITHER_UP_EN(1));
break;
default:
face = screen->face;
break;
}
LcdMskReg(inf, DSP_CTRL0,
m_DISPLAY_FORMAT | m_HSYNC_POLARITY | m_VSYNC_POLARITY | m_DEN_POLARITY |
m_DCLK_POLARITY | m_COLOR_SPACE_CONVERSION,
@@ -540,23 +568,22 @@ void load_screen(struct fb_info *info, bool initscreen)
}
// set lcdc clk
if(SCREEN_MCU==screen->type) screen->pixclock = 150; //mcu fix to 150 MHz
if(SCREEN_MCU==screen->type) screen->pixclock = 150000000; //mcu fix to 150 MHz
clk_set_parent(inf->dclk_divider, inf->dclk_parent);
clk_set_parent(inf->dclk, inf->dclk_divider);
clk_set_parent(inf->aclk, inf->aclk_parent);
dclk_rate = screen->pixclock * 1000000;
fbprintk(">>>>>> set lcdc dclk need %d HZ, clk_parent = %d hz \n ", screen->pixclock, clk_rate);
ret = clk_set_rate(inf->dclk_divider, dclk_rate);
ret = clk_set_rate(inf->dclk_divider, screen->pixclock);
if(ret)
{
printk(KERN_ERR ">>>>>> set lcdc dclk_divider faild \n ");
}
if(screen->lcdc_aclk){
aclk_rate = screen->lcdc_aclk * 1000000;
aclk_rate = screen->lcdc_aclk;
}
ret = clk_set_rate(inf->aclk, aclk_rate);
if(ret){
@@ -1408,7 +1435,7 @@ static int win1fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *inf
struct rk29fb_inf *inf = dev_get_drvdata(info->device);
struct fb_var_screeninfo *var1 = &info->var;
struct fb_fix_screeninfo *fix1 = &info->fix;
int i;
u32 offset = 0, addr = 0;
//fbprintk(">>>>>> %s : %s \n", __FILE__, __FUNCTION__);
@@ -1449,6 +1476,7 @@ static int win1fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *inf
#endif
#if 0
int i;
for(i=0;i<=(0xc0/4);i+=4)
{
fbprintk("0x%02X: 0x%08X 0x%08X 0x%08X 0x%08X \n", i*4,
@@ -1687,7 +1715,7 @@ void resume(struct early_suspend *h)
}
msleep(100);
set_lcd_pin(g_pdev, 1);
memcpy(inf->preg, &inf->regbak, 0xa4); //resume reg
memcpy((u8*)inf->preg, (u8*)&inf->regbak, 0xa4); //resume reg
}
struct suspend_info suspend_info = {

7
drivers/video/rk29_fb.h
View File

@@ -21,14 +21,15 @@
********************************************************************/
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD>ʽ */
#define OUT_P888 0
#define OUT_P666 1
#define OUT_P565 2
#define OUT_P666 1 //666<36><36><EFBFBD><EFBFBD>, <20><>DATA0-17
#define OUT_P565 2 //565<36><35><EFBFBD><EFBFBD>, <20><>DATA0-15
#define OUT_S888x 4
#define OUT_CCIR656 6
#define OUT_S888 8
#define OUT_S888DUMY 12
#define OUT_P16BPP4 24 //ģ<>ⷽʽ,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֧<EFBFBD><D6A7>
#define OUT_D888_P666 0x21 //666<36><36><EFBFBD><EFBFBD>, <20><>DATA2-7, DATA10-15, DATA17-22
#define OUT_D888_P565 0x22 //565<36><35><EFBFBD><EFBFBD>, <20><>DATA3-7, DATA10-15, DATA18-22
/* SYS_CONFIG */
#define m_W2_FORMAT (3<<0)