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FROMLIST: dt-bindings: display: msm: Convert GMU bindings to YAML
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old text bindings. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Link: https://lore.kernel.org/lkml/1582223216-23459-2-git-send-email-jcrouse@codeaurora.org/ Change-Id: I159feb943eafc59551dd5a9d3b02c59679383429
This commit is contained in:
Jordan Crouse
committed by
John Stultz
John Stultz
parent
a9d347b3a5
commit
3d1b35d536
@@ -1,116 +0,0 @@
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Qualcomm adreno/snapdragon GMU (Graphics management unit)
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The GMU is a programmable power controller for the GPU. the CPU controls the
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GMU which in turn handles power controls for the GPU.
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Required properties:
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- compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
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for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
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Note that you need to list the less specific "qcom,adreno-gmu"
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for generic matches and the more specific identifier to identify
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the specific device.
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- reg: Physical base address and length of the GMU registers.
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- reg-names: Matching names for the register regions
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* "gmu"
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* "gmu_pdc"
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* "gmu_pdc_seg"
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- interrupts: The interrupt signals from the GMU.
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- interrupt-names: Matching names for the interrupts
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* "hfi"
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* "gmu"
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- clocks: phandles to the device clocks
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- clock-names: Matching names for the clocks
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* "gmu"
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* "cxo"
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* "axi"
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* "mnoc"
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- power-domains: should be:
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<&clock_gpucc GPU_CX_GDSC>
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<&clock_gpucc GPU_GX_GDSC>
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- power-domain-names: Matching names for the power domains
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- iommus: phandle to the adreno iommu
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- operating-points-v2: phandle to the OPP operating points
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Optional properties:
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- sram: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
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SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.
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Example:
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/ {
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...
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gmu: gmu@506a000 {
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compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
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reg = <0x506a000 0x30000>,
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<0xb280000 0x10000>,
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<0xb480000 0x10000>;
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reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
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interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hfi", "gmu";
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
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clock-names = "gmu", "cxo", "axi", "memnoc";
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power-domains = <&gpucc GPU_CX_GDSC>,
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<&gpucc GPU_GX_GDSC>;
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power-domain-names = "cx", "gx";
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iommus = <&adreno_smmu 5>;
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operating-points-v2 = <&gmu_opp_table>;
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};
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};
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a3xx example with OCMEM support:
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/ {
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...
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gpu: adreno@fdb00000 {
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compatible = "qcom,adreno-330.2",
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"qcom,adreno";
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reg = <0xfdb00000 0x10000>;
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reg-names = "kgsl_3d0_reg_memory";
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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clock-names = "core",
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"iface",
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"mem_iface";
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clocks = <&mmcc OXILI_GFX3D_CLK>,
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<&mmcc OXILICX_AHB_CLK>,
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<&mmcc OXILICX_AXI_CLK>;
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sram = <&gmu_sram>;
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power-domains = <&mmcc OXILICX_GDSC>;
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operating-points-v2 = <&gpu_opp_table>;
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iommus = <&gpu_iommu 0>;
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};
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ocmem@fdd00000 {
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compatible = "qcom,msm8974-ocmem";
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reg = <0xfdd00000 0x2000>,
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<0xfec00000 0x180000>;
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reg-names = "ctrl",
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"mem";
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clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
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<&mmcc OCMEMCX_OCMEMNOC_CLK>;
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clock-names = "core",
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"iface";
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#address-cells = <1>;
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#size-cells = <1>;
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gmu_sram: gmu-sram@0 {
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reg = <0x0 0x100000>;
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ranges = <0 0 0xfec00000 0x100000>;
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};
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};
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};
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130
Documentation/devicetree/bindings/display/msm/gmu.yaml
Normal file
130
Documentation/devicetree/bindings/display/msm/gmu.yaml
Normal file
@@ -0,0 +1,130 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Devicetree bindings for the GMU attached to certain Adreno GPUs
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maintainers:
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- Rob Clark <robdclark@gmail.com>
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description: |
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These bindings describe the Graphics Management Unit (GMU) that is attached
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to members of the Adreno A6xx GPU family. The GMU provides on-device power
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management and support to improve power efficiency and reduce the load on
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the CPU.
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properties:
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compatible:
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items:
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- enum:
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- qcom,adreno-gmu-630.2
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- const: qcom,adreno-gmu
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reg:
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items:
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- description: Core GMU registers
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- description: GMU PDC registers
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- description: GMU PDC sequence registers
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reg-names:
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items:
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- const: gmu
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- const: gmu_pdc
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- const: gmu_pdc_seq
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clocks:
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items:
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- description: GMU clock
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- description: GPU CX clock
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- description: GPU AXI clock
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- description: GPU MEMNOC clock
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clock-names:
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items:
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- const: gmu
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- const: cxo
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- const: axi
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- const: memnoc
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interrupts:
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items:
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- description: GMU HFI interrupt
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- description: GMU interrupt
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interrupt-names:
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items:
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- const: hfi
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- const: gmu
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power-domains:
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items:
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- description: CX power domain
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- description: GX power domain
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power-domain-names:
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items:
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- const: cx
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- const: gx
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iommus:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Phandle to a IOMMU device and stream ID. Refer to ../../iommu/iommu.txt
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for more information.
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operating-points-v2:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the OPP table for the available GMU frequencies. Refer to
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../../opp/opp.txt for more information.
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- power-domains
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- power-domain-names
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- iommus
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- operating-points-v2
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examples:
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- |
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#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gmu: gmu@506a000 {
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compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
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reg = <0x506a000 0x30000>,
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<0xb280000 0x10000>,
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<0xb480000 0x10000>;
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reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
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clock-names = "gmu", "cxo", "axi", "memnoc";
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interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hfi", "gmu";
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power-domains = <&gpucc GPU_CX_GDSC>,
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<&gpucc GPU_GX_GDSC>;
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power-domain-names = "cx", "gx";
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iommus = <&adreno_smmu 5>;
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operating-points-v2 = <&gmu_opp_table>;
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};
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