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arm64: dts: qcom: ipq6018: enable the GICv2m support

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GIC used in the IPQ6018 SoCs has one instance of the GICv2m extension,
which supports upto 32 MSI interrupts. Lets add support for the same.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1644334525-11577-3-git-send-email-quic_kathirav@quicinc.com
This commit is contained in:
Kathiravan T
2022-02-08 21:05:25 +05:30
committed by Bjorn Andersson
parent 59892de947
commit 3d44861d00
1 changed files with 9 additions and 0 deletions
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9
arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -373,6 +373,8 @@
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
#address-cells = <2>;
#size-cells = <2>;
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
@@ -380,6 +382,13 @@
<0x0 0x0b001000 0x0 0x1000>, /*GICH*/
<0x0 0x0b004000 0x0 0x1000>; /*GICV*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
ranges = <0 0 0 0xb00a000 0 0xffd>;
v2m@0 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x0 0x0 0xffd>;
};
};
pcie_phy: phy@84000 {