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media: rockchip: isp: isp39 support unite mode

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Change-Id: Ibea8cbaaf592fc72f6588858a1018b894dd9d495
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2024-02-25 18:09:46 +08:00
committed by Tao Huang
parent 04928950a5
commit 3d9abf9650
5 changed files with 1475 additions and 1297 deletions
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116
drivers/media/platform/rockchip/isp/capture_v39.c
View File

@@ -462,7 +462,8 @@ static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async)
if (dcrop->width == input_win->width &&
dcrop->height == input_win->height &&
dcrop->left == 0 && dcrop->top == 0) {
dcrop->left == 0 && dcrop->top == 0 &&
dev->unite_div < ISP_UNITE_DIV2) {
rkisp_disable_dcrop(stream, async);
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"stream %d crop disabled\n", stream->id);
@@ -608,21 +609,21 @@ static int mp_config_mi(struct rkisp_stream *stream)
*/
val = out_fmt->plane_fmt[0].bytesperline;
val /= DIV_ROUND_UP(fmt->bpp[0], 8);
rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
val *= height;
rkisp_write(dev, stream->config->mi.y_pic_size, val, false);
rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
val = out_fmt->plane_fmt[0].bytesperline * height;
rkisp_write(dev, stream->config->mi.y_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
val = out_fmt->plane_fmt[1].sizeimage;
rkisp_write(dev, stream->config->mi.cb_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
val = out_fmt->plane_fmt[2].sizeimage;
rkisp_write(dev, stream->config->mi.cr_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);
val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_MP_UV_SWAP : 0;
mask = ISP3X_MI_XTD_FORMAT_MP_UV_SWAP;
rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MP_YUV_MODE;
val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -634,24 +635,24 @@ static int mp_config_mi(struct rkisp_stream *stream)
val |= ISP3X_SEPERATE_YUV_CFG;
else
val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_MP_YUV_MODE;
rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false);
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
val = stream->out_isp_fmt.output_format;
rkisp_write(dev, ISP32_MI_MP_WR_CTRL, val, false);
rkisp_unite_write(dev, ISP32_MI_MP_WR_CTRL, val, false);
val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_MP_AUTOUPDATE_ENABLE |
stream->out_isp_fmt.write_format;
mask = GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK;
rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
mi_frame_end_int_enable(stream);
/* set up first buffer */
mi_frame_end(stream, FRAME_INIT);
rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
rkisp_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
return 0;
}
@@ -701,21 +702,21 @@ static int sp_config_mi(struct rkisp_stream *stream)
* memory plane formats, so calculate the size explicitly.
*/
val = stream->u.sp.y_stride;
rkisp_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false);
rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false);
val *= out_fmt->height;
rkisp_write(dev, stream->config->mi.y_pic_size, val, false);
rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
rkisp_write(dev, stream->config->mi.y_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
val = out_fmt->plane_fmt[1].sizeimage;
rkisp_write(dev, stream->config->mi.cb_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
val = out_fmt->plane_fmt[2].sizeimage;
rkisp_write(dev, stream->config->mi.cr_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);
val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_SP_UV_SWAP : 0;
mask = ISP3X_MI_XTD_FORMAT_SP_UV_SWAP;
rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_SP_YUV_MODE;
val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -727,22 +728,22 @@ static int sp_config_mi(struct rkisp_stream *stream)
val |= ISP3X_SEPERATE_YUV_CFG;
else
val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_SP_YUV_MODE;
rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false);
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
CIF_MI_CTRL_INIT_OFFSET_EN | stream->out_isp_fmt.write_format |
sp_in_fmt | stream->out_isp_fmt.output_format |
CIF_MI_SP_AUTOUPDATE_ENABLE;
mask = GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK;
rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
mi_frame_end_int_enable(stream);
/* set up first buffer */
mi_frame_end(stream, FRAME_INIT);
rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
rkisp_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
return 0;
}
@@ -753,18 +754,18 @@ static int ldc_config_mi(struct rkisp_stream *stream)
u32 val;
val = out_fmt->width;
rkisp_write(dev, ISP39_LDCH_OUT_SIZE, val, false);
rkisp_unite_write(dev, ISP39_LDCH_OUT_SIZE, val, false);
val = out_fmt->height;
rkisp_write(dev, ISP39_LDCV_OUT_SIZE, val, false);
rkisp_unite_write(dev, ISP39_LDCV_OUT_SIZE, val, false);
val = out_fmt->plane_fmt[0].bytesperline;
rkisp_write(dev, ISP39_LDCV_WR_STRIDE, val, false);
rkisp_unite_write(dev, ISP39_LDCV_WR_STRIDE, val, false);
mi_frame_end(stream, FRAME_INIT);
rkisp_set_bits(dev, ISP3X_ISP_IMSC, 0, ISP39_LDCV_END, false);
rkisp_unite_set_bits(dev, ISP3X_ISP_IMSC, 0, ISP39_LDCV_END, false);
val = stream->out_isp_fmt.output_format;
if (stream->out_isp_fmt.uv_swap)
val |= ISP39_LDCV_UV_SWAP;
if (val)
rkisp_set_bits(dev, ISP39_LDCV_CTRL, ISP39_LDCV_FORCE_UPD, val, false);
rkisp_unite_set_bits(dev, ISP39_LDCV_CTRL, ISP39_LDCV_FORCE_UPD, val, false);
return 0;
}
@@ -774,7 +775,7 @@ static void mp_enable_mi(struct rkisp_stream *stream)
u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE;
u32 val = CIF_MI_CTRL_MP_ENABLE;
rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
}
static void sp_enable_mi(struct rkisp_stream *stream)
@@ -787,15 +788,15 @@ static void sp_enable_mi(struct rkisp_stream *stream)
if (fmt->fmt_type == FMT_RGB &&
dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
val |= mask;
rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
}
static void ldc_enable_mi(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
rkisp_set_bits(dev, ISP39_LDCV_CTRL, ISP39_LDCV_FORCE_UPD, 1, false);
rkisp_set_bits(dev, ISP3X_LDCH_STS, ISP3X_LDCH_FORCE_UPD, 1, false);
rkisp_unite_set_bits(dev, ISP39_LDCV_CTRL, ISP39_LDCV_FORCE_UPD, 1, false);
rkisp_unite_set_bits(dev, ISP3X_LDCH_STS, ISP3X_LDCH_FORCE_UPD, 1, false);
}
static void mp_disable_mi(struct rkisp_stream *stream)
@@ -803,13 +804,13 @@ static void mp_disable_mi(struct rkisp_stream *stream)
struct rkisp_device *dev = stream->ispdev;
u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE;
rkisp_set_bits(dev, 0x1814, 0, BIT(0), false);
rkisp_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false);
rkisp_unite_set_bits(dev, 0x1814, 0, BIT(0), false);
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false);
}
static void sp_disable_mi(struct rkisp_stream *stream)
{
rkisp_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false);
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false);
}
static void ldc_disable_mi(struct rkisp_stream *stream)
@@ -818,15 +819,17 @@ static void ldc_disable_mi(struct rkisp_stream *stream)
u32 val;
val = ISP3X_LDCH_EN | ISP3X_LDCH_FORCE_UPD;
rkisp_set_bits(dev, ISP3X_LDCH_STS, val, 0, false);
rkisp_unite_set_bits(dev, ISP3X_LDCH_STS, val, 0, false);
val = ISP39_LDCV_EN | ISP39_LDCV_FORCE_UPD;
rkisp_set_bits(dev, ISP39_LDCV_CTRL, val, 0, false);
rkisp_unite_set_bits(dev, ISP39_LDCV_CTRL, val, 0, false);
}
static void update_mi(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
u32 div = stream->out_isp_fmt.fourcc == V4L2_PIX_FMT_UYVY ? 1 : 2;
u32 val, reg;
if (stream->next_buf) {
@@ -843,6 +846,27 @@ static void update_mi(struct rkisp_stream *stream)
val = stream->next_buf->buff_addr[RKISP_PLANE_CR];
rkisp_write(dev, reg, val, false);
}
if (dev->hw_dev->unite > ISP_UNITE_DIV1) {
/* right of image, or right top of image */
reg = stream->config->mi.y_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_Y];
val += ((out_fmt->width / div) & ~0xf);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
reg = stream->config->mi.cb_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CB];
val += ((out_fmt->width / div) & ~0xf);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
if (stream->id != RKISP_STREAM_LDC) {
reg = stream->config->mi.cr_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CR];
val += ((out_fmt->width / div) & ~0xf);
rkisp_idx_write(dev, reg, val, ISP_UNITE_RIGHT, false);
}
}
if (stream->is_pause) {
/* single sensor mode with pingpong buffer:
* if mi on, addr will auto update at frame end
@@ -888,7 +912,7 @@ static void update_mi(struct rkisp_stream *stream)
/* no next buf to preclose mi */
stream->ops->disable_mi(stream);
/* no buf, force to close mi */
if (!stream->curr_buf)
if (!stream->curr_buf && dev->hw_dev->is_single)
stream_self_update(stream);
}
@@ -1618,6 +1642,8 @@ static int rkisp_stream_init(struct rkisp_device *dev, u32 id)
strscpy(vdev->name, SP_VDEV_NAME, sizeof(vdev->name));
stream->ops = &rkisp_sp_streams_ops;
stream->config = &rkisp_sp_stream_cfg;
if (dev->hw_dev->unite)
stream->config->max_rsz_width *= 2;
break;
case RKISP_STREAM_VIR:
strscpy(vdev->name, VIR_VDEV_NAME, sizeof(vdev->name));
@@ -1635,6 +1661,10 @@ static int rkisp_stream_init(struct rkisp_device *dev, u32 id)
strscpy(vdev->name, MP_VDEV_NAME, sizeof(vdev->name));
stream->ops = &rkisp_mp_streams_ops;
stream->config = &rkisp_mp_stream_cfg;
if (dev->hw_dev->unite) {
stream->config->max_rsz_width = CIF_ISP_INPUT_W_MAX_V39_UNITE;
stream->config->max_rsz_height = CIF_ISP_INPUT_H_MAX_V39_UNITE;
}
}
node = vdev_to_node(vdev);
@@ -1706,6 +1736,12 @@ void rkisp_mi_v39_isr(u32 mis_val, struct rkisp_device *dev)
v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
"mi isr:0x%x\n", mis_val);
if ((dev->unite_div == ISP_UNITE_DIV2 && dev->unite_index != ISP_UNITE_RIGHT) ||
(dev->unite_div == ISP_UNITE_DIV4 && dev->unite_index != ISP_UNITE_RIGHT_B)) {
rkisp_write(dev, ISP3X_MI_ICR, mis_val, true);
goto end;
}
for (i = 0; i <= RKISP_STREAM_SP; ++i) {
stream = &dev->cap_dev.stream[i];
@@ -1737,7 +1773,7 @@ void rkisp_mi_v39_isr(u32 mis_val, struct rkisp_device *dev)
mi_frame_end(stream, FRAME_IRQ);
}
}
end:
if (mis_val & ISP3X_MI_MP_FRAME) {
stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
if (!stream->streaming)

2386
drivers/media/platform/rockchip/isp/isp_params_v39.c
View File

File diff suppressed because it is too large Load Diff

181
drivers/media/platform/rockchip/isp/isp_params_v39.h
View File

@@ -22,137 +22,166 @@
struct rkisp_isp_params_vdev;
struct rkisp_isp_params_ops_v39 {
void (*dpcc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_dpcc_cfg *arg);
void (*dpcc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp2x_dpcc_cfg *arg, u32 id);
void (*dpcc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*bls_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_bls_cfg *arg);
void (*bls_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp32_bls_cfg *arg, u32 id);
void (*bls_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*sdg_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_sdg_cfg *arg);
void (*sdg_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp2x_sdg_cfg *arg, u32 id);
void (*sdg_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*lsc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_lsc_cfg *arg);
void (*lsc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp3x_lsc_cfg *arg, u32 id);
void (*lsc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*awbgain_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_awb_gain_cfg *arg);
void (*awbgain_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp32_awb_gain_cfg *arg, u32 id);
void (*awbgain_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*debayer_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_debayer_cfg *arg);
void (*debayer_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_debayer_cfg *arg, u32 id);
void (*debayer_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*ccm_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_ccm_cfg *arg);
void (*ccm_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_ccm_cfg *arg, u32 id);
void (*ccm_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*goc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_gammaout_cfg *arg);
void (*goc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp3x_gammaout_cfg *arg, u32 id);
void (*goc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*cproc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_cproc_cfg *arg);
void (*cproc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp2x_cproc_cfg *arg, u32 id);
void (*cproc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawaf_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_rawaf_meas_cfg *arg);
void (*rawaf_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_rawaf_meas_cfg *arg, u32 id);
void (*rawaf_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawae0_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawaebig_meas_cfg *arg);
void (*rawae0_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp2x_rawaebig_meas_cfg *arg, u32 id);
void (*rawae0_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawae3_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawaebig_meas_cfg *arg);
void (*rawae3_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp2x_rawaebig_meas_cfg *arg, u32 id);
void (*rawae3_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawawb_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_rawawb_meas_cfg *arg);
void (*rawawb_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_rawawb_meas_cfg *arg, u32 id);
void (*rawawb_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawhst0_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawhistbig_cfg *arg);
void (*rawhst0_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp2x_rawhistbig_cfg *arg, u32 id);
void (*rawhst0_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rawhst3_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawhistbig_cfg *arg);
void (*rawhst3_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp2x_rawhistbig_cfg *arg, u32 id);
void (*rawhst3_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*hdrdrc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_drc_cfg *arg,
enum rkisp_params_type type);
void (*hdrdrc_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
enum rkisp_params_type type, u32 id);
void (*hdrdrc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*hdrmge_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_hdrmge_cfg *arg,
enum rkisp_params_type type);
void (*hdrmge_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
enum rkisp_params_type type, u32 id);
void (*hdrmge_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*gic_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_gic_cfg *arg);
void (*gic_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp21_gic_cfg *arg, u32 id);
void (*gic_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*dhaz_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_dhaz_cfg *arg);
void (*dhaz_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_dhaz_cfg *arg, u32 id);
void (*dhaz_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*isp3dlut_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_3dlut_cfg *arg);
void (*isp3dlut_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp2x_3dlut_cfg *arg, u32 id);
void (*isp3dlut_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*ldch_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_ldch_cfg *arg);
void (*ldch_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_ldch_cfg *arg, u32 id);
void (*ldch_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*ynr_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_ynr_cfg *arg);
void (*ynr_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_ynr_cfg *arg, u32 id);
void (*ynr_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*cnr_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_cnr_cfg *arg);
void (*cnr_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_cnr_cfg *arg, u32 id);
void (*cnr_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*sharp_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_sharp_cfg *arg);
void (*sharp_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_sharp_cfg *arg, u32 id);
void (*sharp_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*bay3d_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_bay3d_cfg *arg);
void (*bay3d_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_bay3d_cfg *arg, u32 id);
void (*bay3d_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*gain_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_gain_cfg *arg);
void (*gain_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp3x_gain_cfg *arg, u32 id);
void (*gain_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*cac_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_cac_cfg *arg);
void (*cac_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp32_cac_cfg *arg, u32 id);
void (*cac_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*csm_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_csm_cfg *arg);
const struct isp21_csm_cfg *arg, u32 id);
void (*cgc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_cgc_cfg *arg);
void (*ie_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp21_cgc_cfg *arg, u32 id);
void (*ie_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*yuvme_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_yuvme_cfg *arg);
void (*yuvme_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_yuvme_cfg *arg, u32 id);
void (*yuvme_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*ldcv_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_ldcv_cfg *arg);
void (*ldcv_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_ldcv_cfg *arg, u32 id);
void (*ldcv_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
void (*rgbir_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp39_rgbir_cfg *arg);
void (*rgbir_enable)(struct rkisp_isp_params_vdev *params_vdev, bool en);
const struct isp39_rgbir_cfg *arg, u32 id);
void (*rgbir_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en, u32 id);
};
struct rkisp_isp_params_val_v39 {
struct tasklet_struct lsc_tasklet;
struct rkisp_dummy_buffer buf_3dlut[ISP39_3DLUT_BUF_NUM];
u32 buf_3dlut_idx;
struct rkisp_dummy_buffer buf_3dlut[ISP_UNITE_MAX][ISP39_3DLUT_BUF_NUM];
u32 buf_3dlut_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_ldch[ISP39_MESH_BUF_NUM];
u32 buf_ldch_idx;
struct rkisp_dummy_buffer buf_ldch[ISP_UNITE_MAX][ISP39_MESH_BUF_NUM];
u32 buf_ldch_idx[ISP_UNITE_MAX];
u32 ldch_out_hsize;
struct rkisp_dummy_buffer buf_ldcv[ISP39_MESH_BUF_NUM];
u32 buf_ldcv_idx;
struct rkisp_dummy_buffer buf_ldcv[ISP_UNITE_MAX][ISP39_MESH_BUF_NUM];
u32 buf_ldcv_idx[ISP_UNITE_MAX];
u32 ldcv_out_vsize;
struct rkisp_dummy_buffer buf_cac[ISP39_MESH_BUF_NUM];
u32 buf_cac_idx;
struct rkisp_dummy_buffer buf_cac[ISP_UNITE_MAX][ISP39_MESH_BUF_NUM];
u32 buf_cac_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_info[RKISP_INFO2DDR_BUF_MAX];
u32 buf_info_owner;
u32 buf_info_cnt;
int buf_info_idx;
u32 gain_size;
u32 bay3d_iir_size;
u32 bay3d_cur_size;
struct rkisp_dummy_buffer buf_gain;
struct rkisp_dummy_buffer buf_3dnr_iir;
struct rkisp_dummy_buffer buf_3dnr_cur;
struct rkisp_dummy_buffer buf_frm;
struct isp32_hdrmge_cfg last_hdrmge;
struct isp32_hdrmge_cfg cur_hdrmge;
struct isp39_drc_cfg last_hdrdrc;
struct isp39_drc_cfg cur_hdrdrc;
u32 dhaz_blk_num;
bool dhaz_en;

87
drivers/media/platform/rockchip/isp/isp_stats_v39.c
View File

@@ -111,8 +111,9 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_buffer *buf;
unsigned long flags;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize / dev->unite_div;
u32 val, addr = 0, offset = 0;
int ret = 0;
int i, ret = 0;
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!stats_vdev->nxt_buf && !list_empty(&stats_vdev->stat)) {
@@ -125,44 +126,34 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
if (stats_vdev->nxt_buf) {
addr = stats_vdev->nxt_buf->buff_addr[0];
val = stats_vdev->nxt_buf->buff_addr[0];
rkisp_write(dev, ISP39_W3A_AEBIG_ADDR, val, false);
offset = sizeof(struct isp39_rawae_stat) + sizeof(struct isp39_rawhist_stat);
val += offset;
rkisp_write(dev, ISP39_W3A_AE0_ADDR, val, false);
val += offset;
rkisp_write(dev, ISP39_W3A_AF_ADDR, val, false);
offset = sizeof(struct isp39_rawaf_stat);
val += offset;
rkisp_write(dev, ISP39_W3A_AWB_ADDR, val, false);
if (!dev->hw_dev->is_single) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
} else if (stats_vdev->stats_buf[0].mem_priv) {
addr = stats_vdev->stats_buf[0].dma_addr;
val = stats_vdev->stats_buf[0].dma_addr;
rkisp_write(dev, ISP39_W3A_AEBIG_ADDR, val, false);
offset = sizeof(struct isp39_rawae_stat) + sizeof(struct isp39_rawhist_stat);
val += offset;
rkisp_write(dev, ISP39_W3A_AE0_ADDR, val, false);
val += offset;
rkisp_write(dev, ISP39_W3A_AF_ADDR, val, false);
offset = sizeof(struct isp39_rawaf_stat);
val += offset;
rkisp_write(dev, ISP39_W3A_AWB_ADDR, val, false);
} else {
ret = -EINVAL;
}
if (addr)
if (addr) {
for (i = 0; i < dev->unite_div; i++) {
val = addr + i * size;
rkisp_idx_write(dev, ISP39_W3A_AEBIG_ADDR, val, i, false);
offset = sizeof(struct isp39_rawae_stat) +
sizeof(struct isp39_rawhist_stat);
val += offset;
rkisp_idx_write(dev, ISP39_W3A_AE0_ADDR, val, i, false);
val += offset;
rkisp_idx_write(dev, ISP39_W3A_AF_ADDR, val, i, false);
offset = sizeof(struct isp39_rawaf_stat);
val += offset;
rkisp_idx_write(dev, ISP39_W3A_AWB_ADDR, val, i, false);
}
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s BASE:0x%x SHD AEBIG:0x%x AE0:0x%x AF:0x%x AWB:0x%x\n",
__func__, addr,
@@ -170,6 +161,7 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
isp3_stats_read(stats_vdev, ISP39_W3A_AE0_ADDR_SHD),
isp3_stats_read(stats_vdev, ISP39_W3A_AF_ADDR_SHD),
isp3_stats_read(stats_vdev, ISP39_W3A_AWB_ADDR_SHD));
}
return ret;
}
@@ -255,6 +247,7 @@ rkisp_stats_send_meas_v39(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_isp_readout_work *meas_work)
{
struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev;
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_buffer *cur_buf = stats_vdev->cur_buf;
struct rkisp39_stat_buffer *cur_stat_buf = NULL;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
@@ -271,14 +264,28 @@ rkisp_stats_send_meas_v39(struct rkisp_isp_stats_vdev *stats_vdev,
} else if (cur_buf) {
cur_stat_buf = cur_buf->vaddr[0];
}
/* config buf for next frame */
stats_vdev->cur_buf = NULL;
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
/* buffer done when frame of right handle */
if (dev->unite_div > ISP_UNITE_DIV1) {
if (dev->unite_index == ISP_UNITE_LEFT) {
cur_buf = NULL;
is_dummy = false;
} else if (cur_stat_buf) {
cur_stat_buf = (void *)cur_stat_buf + size / dev->unite_div;
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
}
}
if (dev->unite_div < ISP_UNITE_DIV2 || dev->unite_index == ISP_UNITE_RIGHT) {
/* config buf for next frame */
stats_vdev->cur_buf = NULL;
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
rkisp_stats_update_buf(stats_vdev);
}
rkisp_stats_update_buf(stats_vdev);
cur_frame_id = meas_work->frame_id;
} else {
cur_buf = NULL;
}
@@ -395,7 +402,7 @@ void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
u32 val, size = 0;
u32 val, size = 0, div = dev->unite_div;
if (!stats_vdev->streamon || dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
@@ -411,7 +418,7 @@ void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
v4l2_err(&dev->v4l2_dev, "no stats buf to enable w3a\n");
return;
}
rkisp_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false);
rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false);
val = ISP39_W3A_EN | ISP39_W3A_AUTO_CLR_EN | ISP39_W3A_FORCE_UPD;
if (pdaf_vdev->streaming) {
val |= ISP39_W3A_PDAF_EN;
@@ -421,8 +428,8 @@ void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
pdaf_vdev->next_buf = NULL;
}
}
rkisp_write(dev, ISP39_W3A_CTRL0, val, false);
rkisp_write(dev, ISP39_W3A_WR_SIZE, size, false);
rkisp_unite_write(dev, ISP39_W3A_CTRL0, val, false);
rkisp_unite_write(dev, ISP39_W3A_WR_SIZE, size / div, false);
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;

2
drivers/media/platform/rockchip/isp/rkisp.h
View File

@@ -65,6 +65,8 @@
#define CIF_ISP_INPUT_H_MAX_V32_L_UNITE 6144
#define CIF_ISP_INPUT_W_MAX_V39 4672
#define CIF_ISP_INPUT_H_MAX_V39 3504
#define CIF_ISP_INPUT_W_MAX_V39_UNITE 8192
#define CIF_ISP_INPUT_H_MAX_V39_UNITE 6144
#define CIF_ISP_INPUT_W_MIN 272
#define CIF_ISP_INPUT_H_MIN 272
#define CIF_ISP_OUTPUT_W_MAX CIF_ISP_INPUT_W_MAX