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ARM: dts: rockchip: sort rk3288 dts by base adress
Change-Id: Ibfd497cd8a2dbdbfe4ccb6a35501451926e4fe7e Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This commit is contained in:
Jacob Chen
@@ -1099,6 +1099,26 @@
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status = "disabled";
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};
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cif_isp0: cif_isp@ff910000 {
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compatible = "rockchip,rk3288-cif-isp";
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rockchip,grf = <&grf>;
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reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
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reg-names = "register", "csihost-register";
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clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
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<&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
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<&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
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<&cru SCLK_MIPIDSI_24M>;
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clock-names = "aclk_isp", "hclk_isp",
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"sclk_isp", "sclk_isp_jpe",
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"pclk_mipi_csi", "pclk_isp_in",
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"sclk_mipidsi_24m";
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resets = <&cru SRST_ISP>;
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reset-names = "rst_isp";
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cif_isp10_irq";
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status = "disabled";
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};
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rga: rga@ff920000 {
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compatible = "rockchip,rk3288-rga";
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reg = <0xff920000 0x180>;
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@@ -1330,64 +1350,6 @@
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};
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};
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gpu: gpu@ffa30000 {
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compatible = "arm,malit764",
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"arm,malit76x",
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"arm,malit7xx",
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"arm,mali-midgard";
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reg = <0xffa30000 0x10000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "JOB", "MMU", "GPU";
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clocks = <&cru ACLK_GPU>;
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clock-names = "clk_mali";
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operating-points-v2 = <&gpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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power-domains = <&power RK3288_PD_GPU>;
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status = "disabled";
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gpu_power_model: power_model {
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compatible = "arm,mali-simple-power-model";
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voltage = <950>;
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frequency = <500>;
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static-power = <300>;
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dynamic-power = <396>;
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ts = <32000 4700 (-80) 2>;
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thermal-zone = "gpu_thermal";
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};
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};
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gpu_opp_table: opp-table1 {
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compatible = "operating-points-v2";
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <950000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <950000>;
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};
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opp@300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <1000000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1100000>;
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};
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opp@600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1250000>;
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};
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};
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noc: syscon@ffac0000 {
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compatible = "rockchip,rk3288-noc", "syscon";
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reg = <0xffac0000 0x2000>;
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};
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vpu: video-codec@ff9a0000 {
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compatible = "rockchip,rk3288-vpu";
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reg = <0xff9a0000 0x800>;
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@@ -1473,17 +1435,62 @@
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#iommu-cells = <0>;
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};
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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gpu: gpu@ffa30000 {
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compatible = "arm,malit764",
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"arm,malit76x",
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"arm,malit7xx",
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"arm,mali-midgard";
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reg = <0xffa30000 0x10000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "JOB", "MMU", "GPU";
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clocks = <&cru ACLK_GPU>;
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clock-names = "clk_mali";
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operating-points-v2 = <&gpu_opp_table>;
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#cooling-cells = <2>; /* min followed by max */
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power-domains = <&power RK3288_PD_GPU>;
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status = "disabled";
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reg = <0xffc01000 0x1000>,
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<0xffc02000 0x1000>,
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<0xffc04000 0x2000>,
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<0xffc06000 0x2000>;
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interrupts = <GIC_PPI 9 0xf04>;
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gpu_power_model: power_model {
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compatible = "arm,mali-simple-power-model";
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voltage = <950>;
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frequency = <500>;
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static-power = <300>;
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dynamic-power = <396>;
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ts = <32000 4700 (-80) 2>;
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thermal-zone = "gpu_thermal";
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};
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};
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gpu_opp_table: opp-table1 {
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compatible = "operating-points-v2";
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opp@100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <950000>;
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};
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opp@200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <950000>;
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};
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opp@300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <1000000>;
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};
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opp@400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1100000>;
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};
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opp@600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1250000>;
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};
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};
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noc: syscon@ffac0000 {
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compatible = "rockchip,rk3288-noc", "syscon";
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reg = <0xffac0000 0x2000>;
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};
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efuse: efuse@ffb40000 {
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@@ -1499,24 +1506,17 @@
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};
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};
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cif_isp0: cif_isp@ff910000 {
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compatible = "rockchip,rk3288-cif-isp";
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rockchip,grf = <&grf>;
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reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
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reg-names = "register", "csihost-register";
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clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
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<&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
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<&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
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<&cru SCLK_MIPIDSI_24M>;
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clock-names = "aclk_isp", "hclk_isp",
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"sclk_isp", "sclk_isp_jpe",
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"pclk_mipi_csi", "pclk_isp_in",
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"sclk_mipidsi_24m";
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resets = <&cru SRST_ISP>;
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reset-names = "rst_isp";
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cif_isp10_irq";
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status = "disabled";
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0xffc01000 0x1000>,
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<0xffc02000 0x1000>,
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<0xffc04000 0x2000>,
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<0xffc06000 0x2000>;
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interrupts = <GIC_PPI 9 0xf04>;
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};
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pinctrl: pinctrl {
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