shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: protect the armclk for rk3036

Browse Source 
Some clocks may get disabled as a side effect of another clock
being disabled, because have no consumers. Says the dclk_hdmi's parent may
change from apll to gpll, but the apll's son clocks are very less.

Change-Id: I4fb4e5fdf83a8f73979b50dbcf4f3e4543896fcf
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This commit is contained in:
Caesar Wang
2017-11-17 14:49:16 +08:00
committed by Tao Huang
parent 66a11945da
commit 3ee9576c62
1 changed files with 4 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/clk/rockchip/clk-rk3036.c
View File

@@ -431,6 +431,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
};
static const char *const rk3036_critical_clocks[] __initconst = {
"armclk",
"aclk_cpu",
"aclk_peri",
"hclk_peri",
@@ -497,14 +498,14 @@ static void __init rk3036_clk_init(struct device_node *np)
RK3036_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk3036_clk_branches,
ARRAY_SIZE(rk3036_clk_branches));
rockchip_clk_protect_critical(rk3036_critical_clocks,
ARRAY_SIZE(rk3036_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3036_cpuclk_data, rk3036_cpuclk_rates,
ARRAY_SIZE(rk3036_cpuclk_rates));
rockchip_clk_protect_critical(rk3036_critical_clocks,
ARRAY_SIZE(rk3036_critical_clocks));
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);