phy: rockchip-snps-pcie3: Check the mplla_state/mpllb_state

Change-Id: I5463cace81bb79b6024bc0ac9d0d8de5bfb9ebdb
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2024-09-05 12:35:45 +08:00
committed by Tao Huang
parent 4ca55c87f9
commit 3f258a6c3c

View File

@@ -32,7 +32,8 @@
#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
#define RK3588_SRAM_INIT_DONE(reg) ((reg & 0xff) == 0x49)
#define RK3588_SRAM_INIT_TIMEOUT 20000
struct rockchip_p3phy_ops;
@@ -148,11 +149,14 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
ret = regmap_read_poll_timeout(priv->phy_grf,
RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
reg, RK3588_SRAM_INIT_DONE(reg),
0, 500);
ret |= regmap_read_poll_timeout(priv->phy_grf,
RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
reg, RK3588_SRAM_INIT_DONE(reg),
0, 500);
100, RK3588_SRAM_INIT_TIMEOUT);
if (priv->pcie30_phymode == PHY_MODE_PCIE_AGGREGATION) {
ret |= regmap_read_poll_timeout(priv->phy_grf,
RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
reg, RK3588_SRAM_INIT_DONE(reg),
100, RK3588_SRAM_INIT_TIMEOUT);
}
if (ret)
dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
__func__, reg);