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UPSTREAM: KVM: arm64: Handle host stage-2 faults from 32-bit EL0
When pKVM is enabled, host memory accesses are translated by an identity
mapping at stage-2, which is populated lazily in response to synchronous
exceptions from 64-bit EL1 and EL0.
Extend this handling to cover exceptions originating from 32-bit EL0 as
well. Although these are very unlikely to occur in practice, as the
kernel typically ensures that user pages are initialised before mapping
them in, drivers could still map previously untouched device pages into
userspace and expect things to work rather than panic the system.
Cc: Quentin Perret <qperret@google.com>
Cc: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220427171332.13635-1-will@kernel.org
(cherry picked from commit 2a50fc5fd0)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 233587962
Bug: 233588291
Change-Id: Ibc6ffba7e8b01f940dbe39aefee10be1a7135b5e
This commit is contained in:
@@ -198,15 +198,15 @@ SYM_CODE_START(__kvm_hyp_host_vector)
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invalid_host_el2_vect // FIQ EL2h
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invalid_host_el2_vect // Error EL2h
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host_el1_sync_vect // Synchronous 64-bit EL1
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invalid_host_el1_vect // IRQ 64-bit EL1
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invalid_host_el1_vect // FIQ 64-bit EL1
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invalid_host_el1_vect // Error 64-bit EL1
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host_el1_sync_vect // Synchronous 64-bit EL1/EL0
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invalid_host_el1_vect // IRQ 64-bit EL1/EL0
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invalid_host_el1_vect // FIQ 64-bit EL1/EL0
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invalid_host_el1_vect // Error 64-bit EL1/EL0
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invalid_host_el1_vect // Synchronous 32-bit EL1
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invalid_host_el1_vect // IRQ 32-bit EL1
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invalid_host_el1_vect // FIQ 32-bit EL1
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invalid_host_el1_vect // Error 32-bit EL1
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host_el1_sync_vect // Synchronous 32-bit EL1/EL0
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invalid_host_el1_vect // IRQ 32-bit EL1/EL0
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invalid_host_el1_vect // FIQ 32-bit EL1/EL0
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invalid_host_el1_vect // Error 32-bit EL1/EL0
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SYM_CODE_END(__kvm_hyp_host_vector)
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/*
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