shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 20:07:46 +09:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rockchip: Add RK3588 EVB2 LP4 V10 eDP Board

Browse Source 
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ie3896cf8981a2246f188a6f4411d9acc49f290cb
This commit is contained in:
Wyon Bi
2021-11-22 09:19:20 +08:00
parent 9dce04812e
commit 4074c7cc38
2 changed files with 146 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux-spi-nand.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-edp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb3-lp5-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb3-lp5-v10-edp.dtb

145
arch/arm64/boot/dts/rockchip/rk3588-evb2-lp4-v10-edp.dts Normal file
View File

@@ -0,0 +1,145 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2021 Rockchip Electronics Co., Ltd.
/dts-v1/;
#include "rk3588-evb2-lp4.dtsi"
#include "rk3588-android.dtsi"
/ {
model = "Rockchip RK3588 EVB2 LP4 V10 eDP Board";
compatible = "rockchip,rk3588-evb2-lp4-v10-edp", "rockchip,rk3588";
panel-edp1 {
compatible = "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd>;
prepare-delay-ms = <120>;
enable-delay-ms = <120>;
unprepare-delay-ms = <120>;
disable-delay-ms = <120>;
width-mm = <129>;
height-mm = <171>;
panel-timing {
clock-frequency = <200000000>;
hactive = <1536>;
vactive = <2048>;
hfront-porch = <12>;
hsync-len = <16>;
hback-porch = <48>;
vfront-porch = <8>;
vsync-len = <4>;
vback-porch = <8>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
port {
panel_in_edp1: endpoint {
remote-endpoint = <&edp1_out_panel>;
};
};
};
vcc3v3_lcd: vcc3v3-lcd {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd";
vin-supply = <&vcc_3v3_s0>;
};
};
&backlight {
enable-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
};
&dp0_in_vp0 {
status = "disabled";
};
&dp0_in_vp1 {
status = "okay";
};
&dp0_in_vp2 {
status = "disabled";
};
&dp1_in_vp0 {
status = "disabled";
};
&dp1_in_vp1 {
status = "okay";
};
&dp1_in_vp2 {
status = "disabled";
};
&dsi1 {
status = "disabled";
};
&edp1 {
force-hpd;
status = "okay";
ports {
port@1 {
reg = <1>;
edp1_out_panel: endpoint {
remote-endpoint = <&panel_in_edp1>;
};
};
};
};
&edp1_in_vp0 {
status = "disabled";
};
&edp1_in_vp1 {
status = "disabled";
};
&edp1_in_vp2 {
status = "okay";
};
&gt1x {
status = "disabled";
};
&hdptxphy1 {
status = "okay";
};
&i2c6 {
clock-frequency = <400000>;
status = "okay";
gsl3673@40 {
compatible = "GSL,GSL3673";
reg = <0x40>;
screen_max_x = <1536>;
screen_max_y = <2048>;
irq_gpio_number = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>;
rst_gpio_number = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
};
};
&vcc3v3_lcd_n {
/delete-property/ gpio;
};
&vop {
assigned-clocks = <&cru DCLK_VOP0_SRC>,
<&cru DCLK_VOP1_SRC>,
<&cru DCLK_VOP2_SRC>,
<&cru DCLK_VOP3>;
assigned-clock-parents = <0>, <&cru PLL_GPLL>, <&cru PLL_V0PLL>, <0>;
};