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rk29: L2 cache设置变更。根据IC部的建议，810~972频率，data ram latency设为6 cycles

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黄涛
2010-12-10 18:05:40 +08:00
parent d1d5fd00f5
commit 40a1ab5ca9
1 changed files with 1 additions and 1 deletions
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arch/arm/mm/proc-v7.S
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@@ -272,7 +272,7 @@ __v7_setup:
bic r5, r5, #7 << 6
bic r5, r5, #15
orr r5, r5, #3 << 6 @ Tag RAM latency: b011 = 4 cycles
orr r5, r5, #4 @ Data RAM latency: b0100 = 5 cycles
orr r5, r5, #5 @ Data RAM latency: b0101 = 6 cycles
mcr p15, 1, r5, c9, c0, 2
#endif