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drm/rockchip: vop2: Add delay number for windows

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Change-Id: Id38812958615fb59b7eb60504368383a519592b4
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This commit is contained in:
Andy Yan
2020-12-26 18:47:47 +08:00
committed by Tao Huang
parent 363b2d2f7b
commit 411a740bf9
3 changed files with 53 additions and 3 deletions
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12
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -59,6 +59,16 @@ enum cabc_stage_up_mode {
ADD_MODE,
};
/*
* the delay number of a window in different mode.
*/
enum win_dly_mode {
VOP2_DLY_MODE_DEFAULT, /**< default mode */
VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
VOP2_DLY_MODE_MAX,
};
#define DSP_BG_SWAP 0x1
#define DSP_RB_SWAP 0x2
#define DSP_RG_SWAP 0x4
@@ -631,6 +641,7 @@ struct vop2_win_data {
unsigned int max_upscale_factor;
unsigned int max_downscale_factor;
const uint8_t dly[VOP2_DLY_MODE_MAX];
};
struct vop2_video_port_data {
@@ -740,6 +751,7 @@ struct vop2_ctrl {
struct vop_reg dp_pin_pol;
struct vop_reg win_vp_id[8];
struct vop_reg win_dly[8];
/* connector mux */
struct vop_reg rgb_mux;

32
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -84,9 +84,6 @@
#define VOP_MODULE_SET(vop2, module, name, v) \
REG_SET(vop2, name, 0, module->regs->name, v, false)
#define VOP_REG_SET(vop2, group, name, v) \
vop2_reg_set(vop2, &vop2->data->group->name, 0, ~0, v, #name)
#define VOP_INTR_SET_MASK(vop2, intr, name, mask, v) \
REG_SET_MASK(vop2, name, 0, intr->name, mask, v, false)
@@ -287,6 +284,7 @@ struct vop2_win {
unsigned int max_upscale_factor;
unsigned int max_downscale_factor;
unsigned int supported_rotations;
const uint8_t *dly;
/*
* vertical/horizontal scale up/down filter mode
*/
@@ -3620,6 +3618,32 @@ static void vop2_setup_dly_for_vp(struct vop2_video_port *vp)
VOP_MODULE_SET(vop2, vp, pre_scan_htiming, pre_scan_dly);
}
static void vop2_setup_dly_for_window(struct vop2_video_port *vp, const struct vop2_zpos *vop2_zpos)
{
struct vop2 *vop2 = vp->vop2;
struct vop2_plane_state *vpstate;
const struct vop2_zpos *zpos;
struct drm_plane *plane;
struct vop2_win *win;
uint32_t dly;
int i = 0;
for (i = 0; i < vp->nr_wins; i++) {
zpos = &vop2_zpos[i];
win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
plane = &win->base;
vpstate = to_vop2_plane_state(plane->state);
if (vp->hdr_in && !vp->hdr_out && !vpstate->hdr_in)
dly = win->dly[VOP2_DLY_MODE_HISO_S];
else if (vp->hdr_in && vp->hdr_out && vpstate->hdr_in)
dly = win->dly[VOP2_DLY_MODE_HIHO_H];
else
dly = win->dly[VOP2_DLY_MODE_DEFAULT];
VOP_CTRL_SET(vop2, win_dly[win->phys_id], dly);
}
}
static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state)
{
struct vop2_video_port *vp = to_vop2_video_port(crtc);
@@ -3688,6 +3712,7 @@ static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state
vop2_setup_layer_mixer_for_vp(vp, vop2_zpos);
vop2_setup_alpha(vp, vop2_zpos);
vop2_setup_dly_for_vp(vp);
vop2_setup_dly_for_window(vp, vop2_zpos);
}
/* The pre alpha overlay of Cluster still need process in one win mode. */
@@ -4620,6 +4645,7 @@ static int vop2_win_init(struct vop2 *vop2)
win->hsd_filter_mode = win_data->hsd_filter_mode;
win->vsu_filter_mode = win_data->vsu_filter_mode;
win->vsd_filter_mode = win_data->vsd_filter_mode;
win->dly = win_data->dly;
win->feature = win_data->feature;
win->phys_id = win_data->phys_id;
win->layer_sel_id = win_data->layer_sel_id;

12
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -902,6 +902,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.regs = &rk3568_cluster0_win_data,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.dly = { 0, 27, 21 },
.type = DRM_PLANE_TYPE_OVERLAY,
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
},
@@ -942,6 +943,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.type = DRM_PLANE_TYPE_OVERLAY,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.dly = { 0, 27, 21 },
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
},
@@ -982,6 +984,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.type = DRM_PLANE_TYPE_PRIMARY,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
.dly = { 20, 47, 41 },
},
{
@@ -1002,6 +1005,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.type = DRM_PLANE_TYPE_PRIMARY,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
.dly = { 20, 47, 41 },
},
{
@@ -1022,6 +1026,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.type = DRM_PLANE_TYPE_PRIMARY,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
.dly = { 20, 47, 41 },
},
{
@@ -1042,6 +1047,7 @@ static const struct vop2_win_data rk3568_vop_win_data[] = {
.type = DRM_PLANE_TYPE_OVERLAY,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
.dly = { 20, 47, 41 },
},
};
@@ -1102,6 +1108,12 @@ static const struct vop2_ctrl rk3568_vop_ctrl = {
.win_vp_id[3] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 26),
.win_vp_id[4] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 28),
.win_vp_id[5] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 30),
.win_dly[0] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xff, 0),
.win_dly[1] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xff, 16),
.win_dly[2] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 0),
.win_dly[3] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 8),
.win_dly[4] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 16),
.win_dly[5] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
};
static const struct vop2_data rk3568_vop = {