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arm64: dts: rockchip: rk3576: add cache info for A53/A72

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Change-Id: I984f5ecc8450186822290846a526ae0929bc9035
Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
2025-05-26 16:52:20 +08:00
parent ff148eedd4
commit 424135148b
1 changed files with 74 additions and 0 deletions
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74
arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -296,6 +296,13 @@
#cooling-cells = <2>;
dynamic-power-coefficient = <120>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l>;
};
cpu_l1: cpu@1 {
@@ -307,6 +314,13 @@
clocks = <&scmi_clk ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l>;
};
cpu_l2: cpu@2 {
@@ -318,6 +332,13 @@
clocks = <&scmi_clk ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l>;
};
cpu_l3: cpu@3 {
@@ -329,6 +350,13 @@
clocks = <&scmi_clk ARMCLK_L>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l>;
};
cpu_b0: cpu@100 {
@@ -342,6 +370,13 @@
#cooling-cells = <2>;
dynamic-power-coefficient = <320>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_b>;
};
cpu_b1: cpu@101 {
@@ -353,6 +388,13 @@
clocks = <&scmi_clk ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_b>;
};
cpu_b2: cpu@102 {
@@ -364,6 +406,13 @@
clocks = <&scmi_clk ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_b>;
};
cpu_b3: cpu@103 {
@@ -375,6 +424,31 @@
clocks = <&scmi_clk ARMCLK_B>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_b>;
};
l2_cache_l: l2-cache-cluster0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
l2_cache_b: l2-cache-cluster1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;
};
idle-states {