shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 03:15:31 +09:00
Code Issues Packages Projects Releases Wiki Activity

crypto: rockchip: Fixed the timeout timer being triggered incorrectly

Browse Source 
If the time required for a single data calculation exceeds 3 seconds,
timeout occurs.The timeout timer should be reset after the CRYPTO irq
interrupt is triggered.

Change-Id: I21516ba57bfc8eef3b22624e4ed95523d000cee2
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
This commit is contained in:
Lin Jinhan
2023-07-27 15:38:28 +08:00
parent c19bda6df3
commit 43f141406e
5 changed files with 36 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/crypto/rockchip/rk_crypto_core.c
View File

@@ -272,9 +272,17 @@ static void start_irq_timer(struct rk_crypto_dev *rk_dev)
static void rk_crypto_irq_timer_handle(struct timer_list *t)
{
struct rk_crypto_dev *rk_dev = from_timer(rk_dev, t, timer);
unsigned long flags;
spin_lock_irqsave(&rk_dev->lock, flags);
rk_dev->err = -ETIMEDOUT;
rk_dev->stat.timeout_cnt++;
rk_unload_data(rk_dev);
spin_unlock_irqrestore(&rk_dev->lock, flags);
tasklet_schedule(&rk_dev->done_task);
}
@@ -282,8 +290,12 @@ static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id)
{
struct rk_crypto_dev *rk_dev = platform_get_drvdata(dev_id);
struct rk_alg_ctx *alg_ctx;
unsigned long flags;
spin_lock(&rk_dev->lock);
spin_lock_irqsave(&rk_dev->lock, flags);
/* reset timeout timer */
start_irq_timer(rk_dev);
alg_ctx = rk_alg_ctx_cast(rk_dev->async_req);
@@ -292,9 +304,14 @@ static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id)
if (alg_ctx->ops.irq_handle)
alg_ctx->ops.irq_handle(irq, dev_id);
tasklet_schedule(&rk_dev->done_task);
/* already trigger timeout */
if (rk_dev->err != -ETIMEDOUT) {
spin_unlock_irqrestore(&rk_dev->lock, flags);
tasklet_schedule(&rk_dev->done_task);
} else {
spin_unlock_irqrestore(&rk_dev->lock, flags);
}
spin_unlock(&rk_dev->lock);
return IRQ_HANDLED;
}

4
drivers/crypto/rockchip/rk_crypto_v2_ahash.c
View File

@@ -58,6 +58,10 @@ static void rk_hash_reset(struct rk_crypto_dev *rk_dev)
pool_timeout_us);
CRYPTO_WRITE(rk_dev, CRYPTO_HASH_CTL, 0xffff0000);
/* clear dma int status */
tmp = CRYPTO_READ(rk_dev, CRYPTO_DMA_INT_ST);
CRYPTO_WRITE(rk_dev, CRYPTO_DMA_INT_ST, tmp);
}
static int rk_crypto_irq_handle(int irq, void *dev_id)

4
drivers/crypto/rockchip/rk_crypto_v2_skcipher.c
View File

@@ -197,6 +197,10 @@ static void rk_cipher_reset(struct rk_crypto_dev *rk_dev)
pool_timeout_us);
CRYPTO_WRITE(rk_dev, CRYPTO_BC_CTL, 0xffff0000);
/* clear dma int status */
tmp = CRYPTO_READ(rk_dev, CRYPTO_DMA_INT_ST);
CRYPTO_WRITE(rk_dev, CRYPTO_DMA_INT_ST, tmp);
}
static void rk_crypto_complete(struct crypto_async_request *base, int err)

4
drivers/crypto/rockchip/rk_crypto_v3_ahash.c
View File

@@ -63,6 +63,10 @@ static void rk_hash_reset(struct rk_crypto_dev *rk_dev)
pool_timeout_us);
CRYPTO_WRITE(rk_dev, CRYPTO_HASH_CTL, 0xffff0000);
/* clear dma int status */
tmp = CRYPTO_READ(rk_dev, CRYPTO_DMA_INT_ST);
CRYPTO_WRITE(rk_dev, CRYPTO_DMA_INT_ST, tmp);
}
static int rk_hash_mid_data_store(struct rk_crypto_dev *rk_dev, struct rk_hash_mid_data *mid_data)

4
drivers/crypto/rockchip/rk_crypto_v3_skcipher.c
View File

@@ -196,6 +196,10 @@ static void rk_cipher_reset(struct rk_crypto_dev *rk_dev)
pool_timeout_us);
CRYPTO_WRITE(rk_dev, CRYPTO_BC_CTL, 0xffff0000);
/* clear dma int status */
tmp = CRYPTO_READ(rk_dev, CRYPTO_DMA_INT_ST);
CRYPTO_WRITE(rk_dev, CRYPTO_DMA_INT_ST, tmp);
}
static void rk_crypto_complete(struct crypto_async_request *base, int err)