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Merge tag 'v5.19-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/late

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Amba and clock fixes to conform better to actual dt-bindings.

* tag 'v5.19-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: add clocks property to cru node rk3228
  ARM: dts: rockchip: add clocks property to cru node rk3036
  ARM: dts: rockchip: add clocks property to cru node rk3066a/rk3188
  ARM: dts: rockchip: add clocks property to cru node rk3288
  ARM: dts: rockchip: Remove "amba" bus nodes from rv1108
  ARM: dts: rockchip: add clocks property to cru node rv1108

Link: https://lore.kernel.org/r/4798587.jE0xQCEvom@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-05-27 22:20:31 +02:00
parent 4a4e81ddb8 840fc447d7
commit 440517772b
6 changed files with 23 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/rk3036.dtsi
View File

@@ -330,6 +330,8 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3036-cru";
reg = <0x20000000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;

3
arch/arm/boot/dts/rk3066a.dtsi
View File

@@ -202,8 +202,9 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3066a-cru";
reg = <0x20000000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,

3
arch/arm/boot/dts/rk3188.dtsi
View File

@@ -195,8 +195,9 @@
cru: clock-controller@20000000 {
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};

2
arch/arm/boot/dts/rk322x.dtsi
View File

@@ -484,6 +484,8 @@
cru: clock-controller@110e0000 {
compatible = "rockchip,rk3228-cru";
reg = <0x110e0000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;

2
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -862,6 +862,8 @@
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3288-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;

31
arch/arm/boot/dts/rv1108.dtsi
View File

@@ -85,24 +85,6 @@
#clock-cells = <0>;
};
amba: bus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pdma: pdma@102a0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x102a0000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
};
bus_intmem: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x2000>;
@@ -259,6 +241,17 @@
status = "disabled";
};
pdma: dma-controller@102a0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x102a0000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
grf: syscon@10300000 {
compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
reg = <0x10300000 0x1000>;
@@ -456,6 +449,8 @@
cru: clock-controller@20200000 {
compatible = "rockchip,rv1108-cru";
reg = <0x20200000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;