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video: tegra: correct typeo in HDMI parent clock setup
Change-Id: I7d1d1e8f0e627bc0b2d225af7dde29becc53f991 Signed-off-by: Erik Gilling <konkers@android.com>
This commit is contained in:
committed by
Colin Cross
parent
5318836ea0
commit
44347bbd8b
@@ -494,13 +494,13 @@ void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
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struct clk *pll_d_clk =
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clk_get_sys(NULL, "pll_d");
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if (dc->mode.pclk > 70000)
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if (dc->mode.pclk > 70000000)
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rate = 594000000;
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else
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rate = 216000000;
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if (rate != clk_get_rate(pll_d_clk))
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clk_set_rate(pll_d_clk, rate);
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clk_set_rate(pll_d_clk, rate);
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if (clk_get_parent(clk) != pll_d_out0_clk)
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clk_set_parent(clk, pll_d_out0_clk);
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