video: tegra: correct typeo in HDMI parent clock setup

Change-Id: I7d1d1e8f0e627bc0b2d225af7dde29becc53f991
Signed-off-by: Erik Gilling <konkers@android.com>
This commit is contained in:
Erik Gilling
2010-09-08 17:38:18 -07:00
committed by Colin Cross
parent 5318836ea0
commit 44347bbd8b

View File

@@ -494,13 +494,13 @@ void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
struct clk *pll_d_clk =
clk_get_sys(NULL, "pll_d");
if (dc->mode.pclk > 70000)
if (dc->mode.pclk > 70000000)
rate = 594000000;
else
rate = 216000000;
if (rate != clk_get_rate(pll_d_clk))
clk_set_rate(pll_d_clk, rate);
clk_set_rate(pll_d_clk, rate);
if (clk_get_parent(clk) != pll_d_out0_clk)
clk_set_parent(clk, pll_d_out0_clk);