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clk: x301: cpu hangup when play 3D game [1/1]
PD#SWPL-9471 Problem: it will hangup when play 3D game for a long time Solution: using the origin clk-mux ops to register cpu clock Verify: test passed on x301 Change-Id: I1b977e3a9559ef5f376d4cb8a4735e943c07f525 Signed-off-by: Jian Hu <jian.hu@amlogic.com>
This commit is contained in:
Jian Hu
@@ -402,8 +402,8 @@ static struct meson_clk_mpll tl1_mpll3 = {
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* post-dividers and should be modelled with their respective PLLs via the
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* forthcoming coordinated clock rates feature
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*/
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static u32 mux_table_cpu_p[] = { 0, 1, 2 };
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static u32 mux_table_cpu_px[] = { 0, 1 };
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static u32 mux_table_cpu_p[] = { 0, 1, 2, 3 };
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/*static u32 mux_table_cpu_px[] = { 0, 1 };*/
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static struct meson_cpu_mux_divider tl1_cpu_fclk_p = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL0,
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.cpu_fclk_p00 = {
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@@ -453,20 +453,174 @@ static struct meson_cpu_mux_divider tl1_cpu_fclk_p = {
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},
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};
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static struct meson_clk_cpu tl1_cpu_clk = {
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.reg_off = HHI_SYS_CPU_CLK_CNTL0,
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.clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
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.mux.reg = (void *)HHI_SYS_CPU_CLK_CNTL0,
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.mux.shift = 11,
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.mux.mask = 0x1,
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.mux.lock = &clk_lock,
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.mux.table = mux_table_cpu_px,
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.mux.hw.init = &(struct clk_init_data){
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.name = "cpu_clk",
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.ops = &meson_clk_cpu_ops,
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.parent_names = (const char *[]){ "cpu_fixedpll_p", "sys_pll"},
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/*
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* static struct meson_clk_cpu tl1_cpu_clk = {
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* .reg_off = HHI_SYS_CPU_CLK_CNTL0,
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* .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
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* .mux.reg = (void *)HHI_SYS_CPU_CLK_CNTL0,
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* .mux.shift = 11,
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* .mux.mask = 0x1,
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* .mux.lock = &clk_lock,
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* .mux.table = mux_table_cpu_px,
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* .mux.hw.init = &(struct clk_init_data){
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* .name = "cpu_clk",
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* .ops = &meson_clk_cpu_ops,
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* .parent_names = (const char *[]){ "cpu_fixedpll_p", "sys_pll"},
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* .num_parents = 2,
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* .flags = CLK_GET_RATE_NOCACHE,
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* },
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*};
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*/
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static struct clk_mux tl1_cpu_clk = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL0,
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.mask = 0x1,
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.shift = 11,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk",
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.ops = &clk_mux_ops,
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.parent_names = (const char *[]){ "cpu_fixedpll_p",
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"sys_pll" },
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.num_parents = 2,
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.flags = CLK_GET_RATE_NOCACHE,
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},
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};
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/* dsu clocks */
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static const char * const dsu_fixed_source_sel_parent_names[] = {
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"xtal", "fclk_div2", "fclk_div3", "gp1_pll"
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};
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/* fixed sel0 */
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static struct clk_mux tl1_dsu_fixed_source_sel0 = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x3,
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.shift = 0,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "dsu_fixed_source_sel0",
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.ops = &clk_mux_ops,
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.parent_names = dsu_fixed_source_sel_parent_names,
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.num_parents = ARRAY_SIZE(dsu_fixed_source_sel_parent_names),
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.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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},
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};
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static struct clk_divider tl1_dsu_fixed_source_div0 = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
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.shift = 4,
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.width = 6,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "dsu_fixed_source_div0",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "dsu_fixed_source_sel0" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_mux tl1_dsu_fixed_sel0 = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x1,
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.shift = 2,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "dsu_fixed_sel0",
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.ops = &clk_mux_ops,
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.parent_names = (const char *[]){ "dsu_fixed_source_sel0",
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"dsu_fixed_source_div0" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* fixed sel1 */
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static struct clk_mux tl1_dsu_fixed_source_sel1 = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x3,
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.shift = 16,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "dsu_fixed_source_sel1",
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.ops = &clk_mux_ops,
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.parent_names = dsu_fixed_source_sel_parent_names,
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.num_parents = ARRAY_SIZE(dsu_fixed_source_sel_parent_names),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_divider tl1_dsu_fixed_source_div1 = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
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.shift = 20,
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.width = 6,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "dsu_fixed_source_div1",
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.ops = &clk_divider_ops,
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.parent_names = (const char *[]){ "dsu_fixed_source_sel1" },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_mux tl1_dsu_fixed_sel1 = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x1,
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.shift = 18,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "dsu_fixed_sel1",
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.ops = &clk_mux_ops,
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.parent_names = (const char *[]){ "dsu_fixed_source_sel1",
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"dsu_fixed_source_div1" },
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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/* dsu pre clock parent 0 */
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static struct clk_mux tl1_dsu_pre0_clk = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x1,
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.shift = 10,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "dsu_pre0_clk",
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.ops = &clk_mux_ops,
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.parent_names = (const char *[]){ "dsu_fixed_sel0",
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"dsu_fixed_sel1" },
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.num_parents = 2,
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/* set parent in dsu_fixed_sel0 clk notify */
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.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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},
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};
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static struct clk_mux tl1_dsu_pre_clk = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x1,
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.shift = 11,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "dsu_pre_clk",
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.ops = &clk_mux_ops,
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.parent_names = (const char *[]){ "dsu_pre0_clk", "sys_pll" },
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.num_parents = 2,
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/* dsu_pre0_clk is the only providing clock */
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.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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},
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};
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static struct clk_mux tl1_dsu_clk = {
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.reg = (void *)HHI_SYS_CPU_CLK_CNTL6,
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.mask = 0x1,
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.shift = 27,
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "dsu_clk",
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.ops = &clk_mux_ops,
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.parent_names = (const char *[]){ "cpu_clk", "dsu_pre_clk" },
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.num_parents = 2,
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.flags = CLK_GET_RATE_NOCACHE,
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},
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};
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@@ -717,7 +871,17 @@ static struct clk_hw *tl1_clk_hws[] = {
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[CLKID_SEC_AHB_APB3] = &tl1_sec_ahb_apb3.hw, /*AO 4*/
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[CLKID_CPU_FCLK_P] = &tl1_cpu_fclk_p.hw,
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[CLKID_CPU_CLK] = &tl1_cpu_clk.mux.hw,
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[CLKID_CPU_CLK] = &tl1_cpu_clk.hw,
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[CLKID_DSU_SOURCE_SEL0] = &tl1_dsu_fixed_source_sel0.hw,
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[CLKID_DSU_SOURCE_DIV0] = &tl1_dsu_fixed_source_div0.hw,
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[CLKID_DSU_SEL0] = &tl1_dsu_fixed_sel0.hw,
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[CLKID_DSU_SOURCE_SEL1] = &tl1_dsu_fixed_source_sel1.hw,
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[CLKID_DSU_SOURCE_DIV1] = &tl1_dsu_fixed_source_div1.hw,
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[CLKID_DSU_SEL1] = &tl1_dsu_fixed_sel1.hw,
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[CLKID_DSU_PRE_PARENT0] = &tl1_dsu_pre0_clk.hw,
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[CLKID_DSU_PRE_CLK] = &tl1_dsu_pre_clk.hw,
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[CLKID_DSU_CLK] = &tl1_dsu_clk.hw,
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[CLKID_SWITCH_CLK81] = &tl1_switch_clk81.hw,
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};
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/* Convenience tables to populate base addresses in .probe */
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@@ -812,12 +976,82 @@ static struct clk_gate *tl1_clk_gates[] = {
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&tl1_sec_ahb_apb3,
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};
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struct tl1_nb_data {
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struct notifier_block nb;
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};
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static int tl1_dsu_sel0_clk_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk *dsu_pre0_clk, *parent_clk;
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int ret;
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switch (event) {
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case PRE_RATE_CHANGE:
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parent_clk = tl1_dsu_fixed_sel1.hw.clk;
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break;
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case POST_RATE_CHANGE:
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parent_clk = tl1_dsu_fixed_sel0.hw.clk;
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break;
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default:
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return NOTIFY_DONE;
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}
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dsu_pre0_clk = tl1_dsu_pre0_clk.hw.clk;
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ret = clk_set_parent(dsu_pre0_clk, parent_clk);
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if (ret)
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return notifier_from_errno(ret);
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usleep_range(80, 120);
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return NOTIFY_OK;
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}
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static struct tl1_nb_data tl1_dsu_nb_data = {
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.nb.notifier_call = tl1_dsu_sel0_clk_notifier_cb,
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};
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static int tl1_cpu_clk_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_hw **hws = tl1_clk_hws;
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struct clk_hw *cpu_clk_hw, *parent_clk_hw;
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struct clk *cpu_clk, *parent_clk;
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int ret;
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switch (event) {
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case PRE_RATE_CHANGE:
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parent_clk_hw = hws[CLKID_CPU_FCLK_P];
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break;
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case POST_RATE_CHANGE:
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parent_clk_hw = hws[CLKID_SYS_PLL];
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break;
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default:
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return NOTIFY_DONE;
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}
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cpu_clk_hw = hws[CLKID_CPU_CLK];
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cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw));
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parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw));
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ret = clk_set_parent(cpu_clk, parent_clk);
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if (ret)
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return notifier_from_errno(ret);
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usleep_range(80, 120);
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return NOTIFY_OK;
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}
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static struct notifier_block tl1_cpu_nb_data = {
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.notifier_call = tl1_cpu_clk_notifier_cb,
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};
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static void __init tl1_clkc_init(struct device_node *np)
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{
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int clkid, i;
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int ret = 0;
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struct clk_hw *parent_hw;
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struct clk *parent_clk;
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/* Generic clocks and PLLs */
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clk_base = of_iomap(np, 0);
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@@ -843,9 +1077,8 @@ static void __init tl1_clkc_init(struct device_node *np)
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/* Populate the base address for CPU clk */
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tl1_cpu_fclk_p.reg = clk_base
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+ (unsigned long)tl1_cpu_fclk_p.reg;
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tl1_cpu_clk.base = clk_base;
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tl1_cpu_clk.mux.reg = clk_base
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+ (unsigned long)tl1_cpu_clk.mux.reg;
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tl1_cpu_clk.reg = clk_base
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+ (unsigned long)tl1_cpu_clk.reg;
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/* Populate base address for gates */
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for (i = 0; i < ARRAY_SIZE(tl1_clk_gates); i++)
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@@ -879,9 +1112,30 @@ static void __init tl1_clkc_init(struct device_node *np)
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meson_tl1_gpu_init();
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meson_tl1_misc_init();
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parent_hw = clk_hw_get_parent(&tl1_cpu_clk.mux.hw);
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parent_clk = parent_hw->clk;
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ret = clk_notifier_register(parent_clk, &tl1_cpu_clk.clk_nb);
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/* now cpu clock parent is sys pll , that is to say register
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* sys pll notify clock, why not register tl1_sys_pll.hw derectly?
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*/
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ret = clk_notifier_register(tl1_sys_pll.hw.clk, &tl1_cpu_nb_data);
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/*
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*parent_hw = clk_hw_get_parent(&tl1_cpu_clk.mux.hw);
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*parent_clk = parent_hw->clk;
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*ret = clk_notifier_register(parent_clk, &tl1_cpu_clk.clk_nb);
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*/
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/* set tl1_dsu_fixed_sel1 to 1G (default 24M) */
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ret = clk_set_parent(tl1_dsu_fixed_source_sel1.hw.clk,
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tl1_fclk_div2.hw.clk);
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if (ret < 0) {
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pr_err("%s: failed to set parent for tl1_dsu_fixed_source_sel1\n",
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__func__);
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return;
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}
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/*
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* when change tl1_dsu_fixed_sel0, switch to
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* tl1_dsu_fixed_sel1 to avoid crash
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*/
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ret = clk_notifier_register(tl1_dsu_fixed_sel0.hw.clk,
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&tl1_dsu_nb_data.nb);
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if (ret) {
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pr_err("%s: failed to register clock notifier for cpu_clk\n",
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__func__);
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