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clock-measure: tl1: add clock measurement support
PD#172587: clock-measure: tl1: add clock measurement support Change-Id: I14ab8859b205154bb89139e215fef5898efac681 Signed-off-by: Jian Hu <jian.hu@amlogic.com>
This commit is contained in:
Jian Hu
@@ -21,6 +21,7 @@ Required Properties:
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"amlogic,g12b-aoclkc" - for g12b ao clock
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"amlogic,tl1-clkc" - for tl1 ee clock
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"amlogic,tl1-aoclkc" - for tl1 ao clock
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"amlogic,tl1-measure" - for tl1 clock measurement
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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@@ -36,6 +36,7 @@
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#include <linux/amlogic/clk_measure.h>
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#include <linux/amlogic/scpi_protocol.h>
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#include <linux/spinlock.h>
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#include <linux/of_device.h>
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#undef pr_fmt
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#define pr_fmt(fmt) "clkmsr: " fmt
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@@ -54,6 +55,16 @@ unsigned int clk_msr_index = 0xff;
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#define AO_RTI_PIN_MUX_REG1 0x18
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unsigned int audio_index;
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struct meson_clkmsr_data {
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const char * const *clk_table;
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unsigned int table_size;
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unsigned int (*clk_msr_function)(unsigned int clk_mux);
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/* sentinel maybe new diference between deferent SoCs */
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};
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static struct meson_clkmsr_data *clk_data;
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static unsigned int m8b_clk_util_clk_msr(unsigned int clk_mux)
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{
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unsigned int msr;
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@@ -1194,25 +1205,29 @@ int meson_clk_measure(unsigned int clk_mux)
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unsigned long flags;
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spin_lock_irqsave(&clk_measure_lock, flags);
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switch (get_cpu_type()) {
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case MESON_CPU_MAJOR_ID_M8B:
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clk_val = m8b_clk_util_clk_msr(clk_mux);
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break;
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case MESON_CPU_MAJOR_ID_GXL:
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case MESON_CPU_MAJOR_ID_GXM:
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case MESON_CPU_MAJOR_ID_TXL:
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case MESON_CPU_MAJOR_ID_TXLX:
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case MESON_CPU_MAJOR_ID_G12A:
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case MESON_CPU_MAJOR_ID_G12B:
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clk_val = gxbb_clk_util_clk_msr(clk_mux);
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break;
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case MESON_CPU_MAJOR_ID_AXG:
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clk_val = axg_clk_util_clk_msr(clk_mux);
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break;
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default:
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pr_info("Unsupported chip clk measure\n");
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clk_val = 0;
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break;
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if (clk_data) {
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clk_val = clk_data->clk_msr_function(clk_mux);
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} else {
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switch (get_cpu_type()) {
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case MESON_CPU_MAJOR_ID_M8B:
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clk_val = m8b_clk_util_clk_msr(clk_mux);
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break;
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case MESON_CPU_MAJOR_ID_GXL:
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case MESON_CPU_MAJOR_ID_GXM:
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case MESON_CPU_MAJOR_ID_TXL:
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case MESON_CPU_MAJOR_ID_TXLX:
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case MESON_CPU_MAJOR_ID_G12A:
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case MESON_CPU_MAJOR_ID_G12B:
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clk_val = gxbb_clk_util_clk_msr(clk_mux);
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break;
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case MESON_CPU_MAJOR_ID_AXG:
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clk_val = axg_clk_util_clk_msr(clk_mux);
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break;
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default:
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pr_info("Unsupported chip clk measure\n");
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clk_val = 0;
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break;
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}
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}
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spin_unlock_irqrestore(&clk_measure_lock, flags);
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@@ -1223,22 +1238,33 @@ EXPORT_SYMBOL(meson_clk_measure);
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static int dump_clk(struct seq_file *s, void *what)
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{
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if (get_cpu_type() == MESON_CPU_MAJOR_ID_M8B)
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m8b_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXL)
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gxl_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM)
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gxm_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_AXG)
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axg_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TXL)
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txl_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TXLX)
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txlx_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A)
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g12a_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12B)
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g12b_clk_measure(s, what, clk_msr_index);
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if (clk_data) {
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int i;
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const char * const *clk_table = clk_data->clk_table;
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int len = clk_data->table_size;
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for (i = 0; i < len; i++)
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seq_printf(s, "[%2d][%10d]%s\n", i,
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clk_data->clk_msr_function(i), clk_table[i]);
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} else {
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if (get_cpu_type() == MESON_CPU_MAJOR_ID_M8B)
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m8b_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXL)
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gxl_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_GXM)
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gxm_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_AXG)
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axg_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TXL)
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txl_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TXLX)
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txlx_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A)
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g12a_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12B)
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g12b_clk_measure(s, what, clk_msr_index);
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}
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return 0;
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}
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@@ -1342,12 +1368,171 @@ static int aml_clkmsr_probe(struct platform_device *pdev)
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pr_info("msr_ring_reg0=%p\n", msr_ring_reg0);
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}
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clk_data = (struct meson_clkmsr_data *)
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of_device_get_match_data(&pdev->dev);
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return 0;
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}
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static const char * const tl1_table[] = {
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[144] = "ts_pll_clk",
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[143] = "mainclk",
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[142] = "demode_ts_clk",
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[141] = "ts_ddr_clk",
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[140] = "audio_toacodec_bclk",
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[139] = "aud_adc_clk_g128x",
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[138] = "dsu_pll_clk_cpu",
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[137] = "atv_dmd_i2c_sclk",
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[136] = "sys_pll_clk",
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[135] = "tvfe_sample_clk",
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[134] = "adc_extclk_in",
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[133] = "atv_dmd_mono_clk_32",
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[132] = "audio_toacode_mclk",
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[131] = "ts_sar_clk",
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[130] = "au_dac2_clk_gf128x",
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[129] = "lvds_fifo_clk",
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[128] = "cts_tcon_pll_clk",
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[127] = "hdmirx_vid_clk",
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[126] = "sar_ring_osc_clk",
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[125] = "cts_hdmi_axi_clk",
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[124] = "cts_demod_core_clk",
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[123] = "mod_audio_pdm_dclk_o",
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[122] = "audio_spdifin_mst_clk",
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[121] = "audio_spdifout_mst_clk",
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[120] = "audio_spdifout_b_mst_clk",
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[119] = "audio_pdm_sysclk",
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[118] = "audio_resamplea_clk",
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[117] = "audio_resampleb_clk",
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[116] = "audio_tdmin_a_sclk",
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[115] = "audio_tdmin_b_sclk",
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[114] = "audio_tdmin_c_sclk",
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[113] = "audio_tdmin_lb_sclk",
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[112] = "audio_tdmout_a_sclk",
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[111] = "audio_tdmout_b_sclk",
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[110] = "audio_tdmout_c_sclk",
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[109] = "o_vad_clk",
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[108] = "acodec_i2sout_bclk",
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[107] = "au_dac_clk_g128x",
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[106] = "ephy_test_clk",
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[105] = "am_ring_osc_clk_out_ee[9]",
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[104] = "am_ring_osc_clk_out_ee[8]",
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[103] = "am_ring_osc_clk_out_ee[7]",
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[102] = "am_ring_osc_clk_out_ee[6]",
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[101] = "am_ring_osc_clk_out_ee[5]",
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[100] = "am_ring_osc_clk_out_ee[4]",
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[99] = "am_ring_osc_clk_out_ee[3]",
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[98] = "cts_ts_clk",
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[97] = "cts_vpu_clkb_tmp",
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[96] = "cts_vpu_clkb",
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[95] = "eth_phy_plltxclk",
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[94] = "eth_phy_exclk",
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[93] = "sys_cpu_ring_osc_clk[3]",
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[92] = "sys_cpu_ring_osc_clk[2]",
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[91] = "hdmirx_audmeas_clk",
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[90] = "am_ring_osc_clk_out_ee[11]",
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[89] = "am_ring_osc_clk_out_ee[10]",
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[88] = "cts_hdmirx_meter_clk",
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[87] = "1'b0",
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[86] = "cts_hdmirx_modet_clk",
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[85] = "cts_hdmirx_acr_ref_clk",
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[84] = "co_tx_cl",
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[83] = "co_rx_clk",
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[82] = "cts_ge2d_clk",
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[81] = "cts_vapbclk",
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[80] = "rng_ring_osc_clk[3]",
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[79] = "rng_ring_osc_clk[2]",
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[78] = "rng_ring_osc_clk[1]",
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[77] = "rng_ring_osc_clk[0]",
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[76] = "hdmix_aud_clk",
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[75] = "cts_hevcf_clk",
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[74] = "hdmirx_aud_pll_clk",
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[73] = "cts_pwm_C_clk",
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[72] = "cts_pwm_D_clk",
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[71] = "cts_pwm_E_clk",
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[70] = "cts_pwm_F_clk",
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[69] = "cts_hdcp22_skpclk",
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[68] = "cts_hdcp22_esmclk",
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[67] = "hdmirx_apll_clk_audio",
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[66] = "cts_vid_lock_clk",
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[65] = "cts_spicc_0_clk",
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[64] = "cts_spicc_1_clk",
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[63] = "hdmirx_tmds_clk",
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[62] = "cts_hevcb_clk",
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[61] = "gpio_clk_msr",
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[60] = "cts_hdmirx_aud_pll_clk",
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[59] = "cts_hcodec_clk",
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[58] = "cts_vafe_datack",
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[57] = "cts_atv_dmd_vdac_clk",
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[56] = "cts_atv_dmd_sys_clk",
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[55] = "vid_pll_div_clk_out",
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[54] = "cts_vpu_clkc",
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[53] = "ddr_2xclk",
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[52] = "cts_sd_emmc_clk_B",
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[51] = "cts_sd_emmc_clk_C",
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[50] = "mp3_clk_out",
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[49] = "mp2_clk_out",
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[48] = "mp1_clk_out",
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[47] = "ddr_dpll_pt_clk",
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[46] = "cts_vpu_clk",
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[45] = "cts_pwm_A_clk",
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[44] = "cts_pwm_B_clk",
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[43] = "fclk_div5",
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[42] = "mp0_clk_out",
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[41] = "mac_eth_rx_clk_rmii",
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[40] = "cts_hdmirx_cfg_clk",
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[39] = "cts_bt656_clk0",
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[38] = "cts_vdin_meas_clk",
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[37] = "cts_cdac_clk_c",
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[36] = "cts_hdmi_tx_pixel_clk",
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[35] = "cts_mali_clk",
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[34] = "eth_mppll_50m_ckout",
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[33] = "sys_cpu_ring_osc_clk[1]",
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[32] = "cts_vdec_clk",
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[31] = "mpll_clk_test_out",
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[30] = "hdmirx_cable_clk",
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[29] = "hdmirx_apll_clk_out_div",
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[28] = "cts_sar_adc_clk",
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[27] = "co_clkin_to_mac",
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[26] = "sc_clk_int",
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[25] = "cts_eth_clk_rmii",
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[24] = "cts_eth_clk125Mhz",
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[23] = "mpll_clk_50m",
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[22] = "mac_eth_phy_ref_clk",
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[21] = "lcd_an_clk_ph3",
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[20] = "rtc_osc_clk_out",
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[19] = "lcd_an_clk_ph2",
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[18] = "sys_cpu_clk_div16",
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[17] = "sys_pll_div16",
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[16] = "cts_FEC_CLK_2",
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[15] = "cts_FEC_CLK_1",
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[14] = "cts_FEC_CLK_0",
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[13] = "mod_tcon_clko",
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[12] = "hifi_pll_clk",
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[11] = "mac_eth_tx_clk",
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[10] = "cts_vdac_clk",
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[9] = "cts_encl_clk",
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[8] = "cts_encp_clk",
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[7] = "clk81",
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[6] = "cts_enci_clk",
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[5] = "gp1_pll_clk",
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[4] = "gp0_pll_clk",
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[3] = "sys_cpu_ring_osc_clk[0]",
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[2] = "am_ring_osc_clk_out_ee[2]",
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[1] = "am_ring_osc_clk_out_ee[1]",
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[0] = "am_ring_osc_clk_out_ee[0]",
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};
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static const struct meson_clkmsr_data tl1_data = {
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.clk_table = tl1_table,
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.table_size = ARRAY_SIZE(tl1_table),
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.clk_msr_function = gxbb_clk_util_clk_msr,
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};
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static const struct of_device_id meson_clkmsr_dt_match[] = {
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{ .compatible = "amlogic, gxl_measure",},
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{ .compatible = "amlogic, m8b_measure",},
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{ .compatible = "amlogic,tl1-measure", .data = &tl1_data },
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{},
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};
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