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ARM: errata: Workaround for Cortex-A12 erratum 821420

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On Cortex-A12 (r0p0, r0p1), in very rare timing conditions, a sequence of
VMOV to Core registers instructions, for which the second one is in the
shadow of a branch or abort, can lead to a deadlock when the VMOV
instructions are issued out-of-order. This workaround setting bit 1 of
the Internal Feature Register prevents the erratum.

Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
This commit is contained in:
Huang, Tao
2015-01-06 10:08:16 +08:00
parent bb70e88099
commit 452b07f879
2 changed files with 18 additions and 0 deletions
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10
arch/arm/Kconfig
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@@ -1373,6 +1373,16 @@ config ARM_ERRATA_818325
prevents the erratum. This bit disables an optimisation applied to a
sequence of 2 instructions that use opposing condition codes.
config ARM_ERRATA_821420
bool "ARM errata: A sequence of VMOV to core registers instruction might lead to a deadlock"
depends on CPU_V7
help
This option enables the workaround for the 821420 Cortex-A12 (r0p0,
r0p1) erratum. In very rare timing conditions, a sequence of VMOV to
Core registers instructions, for which the second one is in the
shadow of a branch or abort, can lead to a deadlock when the VMOV
instructions are issued out-of-order.
endmenu
source "arch/arm/common/Kconfig"

8
arch/arm/mm/proc-v7.S
View File

@@ -340,6 +340,14 @@ __v7_setup:
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
isb
#endif
#ifdef CONFIG_ARM_ERRATA_821420
teq r6, #0x00 @ present in r0p0
teqne r6, #0x01 @ present in r0p1
mrceq p15, 0, r10, c15, c0, 2
orreq r10, r10, #1 << 1
mcreq p15, 0, r10, c15, c0, 2
isb
#endif
4: mov r10, #0
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate