drm: add TL1 drm support [1/1]

PD#SWPL-7987

Problem:
TL1 DRM support

Solution:
add TL1 DRM support

Verify:
t962x2_x301

Change-Id: Ibc8ff641f42c0a416e80c3a420c1d808e0ad8b26
Signed-off-by: Dezhi Kong <dezhi.kong@amlogic.com>

MAINTAINERS

@@ -15034,3 +15034,17 @@ AMLOGIC DRM
 M:	Ao Xu <ao.xu@amlogic.com>
 F:	drivers/amlogic/drm/meson_debugfs.c
 
+AMLOGIC DRM
+M:	Dezhi Kong <dezhi.kong@amlogic.com>
+F:	arch/arm/boot/dts/amlogic/mesontl1_drm.dtsi
+F:	arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g_drm.dts
+F:	arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g_drm.dts
+F:	arch/arm64/boot/dts/amlogic/mesontl1_drm.dtsi
+F:	arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g_drm.dts
+F:	arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g_drm.dts
+F:	drivers/amlogic/drm/meson_lcd.c
+F:	drivers/amlogic/drm/meson_vpu.c
+F:	drivers/amlogic/drm/meson_vpu_pipeline.c
+F:	drivers/amlogic/drm/meson_vpu_pipeline_traverse.c
+F:	include/dt-bindings/display/meson-drm-ids.h
+

arch/arm/boot/dts/amlogic/mesontl1_drm.dtsi

@@ -0,0 +1,211 @@
+/*
+ * arch/arm/boot/dts/amlogic/meson_drm.dtsi
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+#include <dt-bindings/display/meson-drm-ids.h>
+
+/ {
+	venc-cvbs {
+		status = "okay";
+		compatible = "amlogic, meson-tl1-cvbs";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			enc_cvbs_in: port@0 {
+				 #address-cells = <1>;
+				 #size-cells = <0>;
+				 reg = <0>;
+
+				 //venc_cvbs_in_vpu: endpoint@0 {
+				//	 reg = <0>;
+				//	 remote-endpoint = <&vpu_out_venc_cvbs>;
+				//};
+			};
+		};
+	};
+
+	drm_amhdmitx: drm-amhdmitx {
+		status = "disabled";
+		hdcp = "disabled";
+		compatible = "amlogic,drm-amhdmitx";
+		dev_name = "meson-amhdmitx";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
+		ports {
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				hdmi_in_vpu: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vpu_out_hdmi>;
+				};
+			};
+		};
+	};
+
+	drm_lcd: drm-lcd {
+		status = "disabled";
+		compatible = "amlogic,drm-lcd";
+		dev_name = "meson-lcd";
+		ports {
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				lcd_in_vpu: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vpu_out_lcd>;
+				};
+			};
+		};
+	};
+
+	drm_vpu: drm-vpu@0xff900000  {
+		status = "disabled";
+		compatible = "amlogic, meson-tl1-vpu";
+		memory-region = <&logo_reserved>;
+		reg = <0xff900000 0x40000>,
+			  <0xff63c000 0x2000>,
+			  <0xff638000 0x2000>;
+		reg-names = "base", "hhi", "dmc";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "viu-vsync", "viu2-vsync";
+		clocks = <&clkc CLKID_VPU_CLKC_MUX>;
+		clock-names = "vpu_clkc";
+		dma-coherent;
+		vpu_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vpu_out_hdmi: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&hdmi_in_vpu>;
+			};
+			vpu_out_lcd: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&lcd_in_vpu>;
+			};
+		};
+	};
+
+	drm_subsystem: drm-subsystem {
+		status = "okay";
+		compatible = "amlogic,drm-subsystem";
+		ports = <&vpu_out>;
+
+		vpu_topology: vpu_topology {
+			vpu_blocks {
+				osd1_block: block@0 {
+					id = /bits/ 8 <OSD1_BLOCK>;
+					index = /bits/ 8  <0>;
+					type = /bits/ 8  <0>;
+					block_name = "osd1_block";
+					num_in_links = /bits/ 8  <0x0>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &afbc_osd1_block>;
+				};
+				osd2_block: block@1 {
+					id = /bits/ 8  <OSD2_BLOCK>;
+					index = /bits/ 8  <1>;
+					type = /bits/ 8  <0>;
+					block_name = "osd2_block";
+					num_in_links = /bits/ 8  <0x0>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &afbc_osd2_block>;
+				};
+				afbc_osd1_block: block@3 {
+					id = /bits/ 8  <AFBC_OSD1_BLOCK>;
+					index = /bits/ 8  <0>;
+					type = /bits/ 8  <1>;
+					block_name = "afbc_osd1_block";
+					num_in_links = /bits/ 8  <0x1>;
+					in_links = <0 &osd1_block>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &osd_blend_block>;
+				};
+				afbc_osd2_block: block@4 {
+					id = /bits/ 8  <AFBC_OSD2_BLOCK>;
+					index = /bits/ 8  <1>;
+					type = /bits/ 8  <1>;
+					block_name = "afbc_osd2_block";
+					num_in_links = /bits/ 8  <0x1>;
+					in_links = <0 &osd2_block>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &scaler_osd2_block>;
+				};
+				scaler_osd1_block: block@6 {
+					id = /bits/ 8  <SCALER_OSD1_BLOCK>;
+					index = /bits/ 8  <0>;
+					type = /bits/ 8  <2>;
+					block_name = "scaler_osd1_block";
+					num_in_links = /bits/ 8  <0x1>;
+					in_links = <0 &osd1_hdr_dolby_block>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &vpp_postblend_block>;
+				};
+				scaler_osd2_block: block@7 {
+					id = /bits/ 8  <SCALER_OSD2_BLOCK>;
+					index = /bits/ 8  <1>;
+					type = /bits/ 8  <2>;
+					block_name = "scaler_osd2_block";
+					num_in_links = /bits/ 8  <0x1>;
+					in_links = <0 &afbc_osd2_block>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <2 &osd_blend_block>;
+				};
+				osd_blend_block: block@9 {
+					id = /bits/ 8  <OSD_BLEND_BLOCK>;
+					block_name = "osd_blend_block";
+					type = /bits/ 8  <3>;
+					num_in_links = /bits/ 8  <0x2>;
+					in_links = <0 &afbc_osd1_block>,
+						<0 &scaler_osd2_block>;
+					num_out_links = /bits/ 8  <0x2>;
+					out_links = <0 &osd1_hdr_dolby_block>,
+						<1 &vpp_postblend_block>;
+				};
+				osd1_hdr_dolby_block: block@10 {
+					id = /bits/ 8  <OSD1_HDR_BLOCK>;
+					block_name = "osd1_hdr_dolby_block";
+					type = /bits/ 8  <4>;
+					num_in_links = /bits/ 8  <0x1>;
+					in_links = <0 &osd_blend_block>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &scaler_osd1_block>;
+				};
+				vpp_postblend_block: block@12 {
+					id = /bits/ 8  <VPP_POSTBLEND_BLOCK>;
+					block_name = "vpp_postblend_block";
+					type = /bits/ 8  <6>;
+					num_in_links = /bits/ 8  <0x2>;
+					in_links = <0 &scaler_osd1_block>,
+						<1 &osd_blend_block>;
+					num_out_links = <0x0>;
+				};
+			};
+		};
+
+		vpu_hw_para: vpu_hw_para@0 {
+			osd_ver = /bits/ 8 <0x2>;
+			afbc_type = /bits/ 8 <0x2>;
+			has_deband = /bits/ 8 <0x1>;
+			has_lut = /bits/ 8 <0x1>;
+			has_rdma = /bits/ 8 <0x1>;
+			osd_fifo_len = /bits/ 8 <64>;
+			vpp_fifo_len = /bits/ 32 <0xfff>;
+		};
+	};
+};

arch/arm64/boot/dts/amlogic/mesontl1_drm.dtsi

@@ -0,0 +1,211 @@
+/*
+ * arch/arm64/boot/dts/amlogic/mesontl1_drm.dtsi
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+#include <dt-bindings/display/meson-drm-ids.h>
+
+/ {
+	venc-cvbs {
+		status = "okay";
+		compatible = "amlogic, meson-tl1-cvbs";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			enc_cvbs_in: port@0 {
+				 #address-cells = <1>;
+				 #size-cells = <0>;
+				 reg = <0>;
+
+				 //venc_cvbs_in_vpu: endpoint@0 {
+				//	 reg = <0>;
+				//	 remote-endpoint = <&vpu_out_venc_cvbs>;
+				//};
+			};
+		};
+	};
+
+	drm_amhdmitx: drm-amhdmitx {
+		status = "disabled";
+		hdcp = "disabled";
+		compatible = "amlogic,drm-amhdmitx";
+		dev_name = "meson-amhdmitx";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
+		ports {
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				hdmi_in_vpu: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vpu_out_hdmi>;
+				};
+			};
+		};
+	};
+
+	drm_lcd: drm-lcd {
+		status = "disabled";
+		compatible = "amlogic,drm-lcd";
+		dev_name = "meson-lcd";
+		ports {
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				lcd_in_vpu: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vpu_out_lcd>;
+				};
+			};
+		};
+	};
+
+	drm_vpu: drm-vpu@0xff900000  {
+		status = "disabled";
+		compatible = "amlogic, meson-tl1-vpu";
+		memory-region = <&logo_reserved>;
+		reg = <0x0 0xff900000 0x0 0x40000>,
+			  <0x0 0xff63c000 0x0 0x2000>,
+			  <0x0 0xff638000 0x0 0x2000>;
+		reg-names = "base", "hhi", "dmc";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "viu-vsync", "viu2-vsync";
+		clocks = <&clkc CLKID_VPU_CLKC_MUX>;
+		clock-names = "vpu_clkc";
+		dma-coherent;
+		vpu_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vpu_out_hdmi: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&hdmi_in_vpu>;
+			};
+			vpu_out_lcd: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&lcd_in_vpu>;
+			};
+		};
+	};
+
+	drm_subsystem: drm-subsystem {
+		status = "okay";
+		compatible = "amlogic,drm-subsystem";
+		ports = <&vpu_out>;
+
+		vpu_topology: vpu_topology {
+			vpu_blocks {
+				osd1_block: block@0 {
+					id = /bits/ 8 <OSD1_BLOCK>;
+					index = /bits/ 8  <0>;
+					type = /bits/ 8  <0>;
+					block_name = "osd1_block";
+					num_in_links = /bits/ 8  <0x0>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &afbc_osd1_block>;
+				};
+				osd2_block: block@1 {
+					id = /bits/ 8  <OSD2_BLOCK>;
+					index = /bits/ 8  <1>;
+					type = /bits/ 8  <0>;
+					block_name = "osd2_block";
+					num_in_links = /bits/ 8  <0x0>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &afbc_osd2_block>;
+				};
+				afbc_osd1_block: block@3 {
+					id = /bits/ 8  <AFBC_OSD1_BLOCK>;
+					index = /bits/ 8  <0>;
+					type = /bits/ 8  <1>;
+					block_name = "afbc_osd1_block";
+					num_in_links = /bits/ 8  <0x1>;
+					in_links = <0 &osd1_block>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &osd_blend_block>;
+				};
+				afbc_osd2_block: block@4 {
+					id = /bits/ 8  <AFBC_OSD2_BLOCK>;
+					index = /bits/ 8  <1>;
+					type = /bits/ 8  <1>;
+					block_name = "afbc_osd2_block";
+					num_in_links = /bits/ 8  <0x1>;
+					in_links = <0 &osd2_block>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &scaler_osd2_block>;
+				};
+				scaler_osd1_block: block@6 {
+					id = /bits/ 8  <SCALER_OSD1_BLOCK>;
+					index = /bits/ 8  <0>;
+					type = /bits/ 8  <2>;
+					block_name = "scaler_osd1_block";
+					num_in_links = /bits/ 8  <0x1>;
+					in_links = <0 &osd1_hdr_dolby_block>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &vpp_postblend_block>;
+				};
+				scaler_osd2_block: block@7 {
+					id = /bits/ 8  <SCALER_OSD2_BLOCK>;
+					index = /bits/ 8  <1>;
+					type = /bits/ 8  <2>;
+					block_name = "scaler_osd2_block";
+					num_in_links = /bits/ 8  <0x1>;
+					in_links = <0 &afbc_osd2_block>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <2 &osd_blend_block>;
+				};
+				osd_blend_block: block@9 {
+					id = /bits/ 8  <OSD_BLEND_BLOCK>;
+					block_name = "osd_blend_block";
+					type = /bits/ 8  <3>;
+					num_in_links = /bits/ 8  <0x2>;
+					in_links = <0 &afbc_osd1_block>,
+						<0 &scaler_osd2_block>;
+					num_out_links = /bits/ 8  <0x2>;
+					out_links = <0 &osd1_hdr_dolby_block>,
+						<1 &vpp_postblend_block>;
+				};
+				osd1_hdr_dolby_block: block@10 {
+					id = /bits/ 8  <OSD1_HDR_BLOCK>;
+					block_name = "osd1_hdr_dolby_block";
+					type = /bits/ 8  <4>;
+					num_in_links = /bits/ 8  <0x1>;
+					in_links = <0 &osd_blend_block>;
+					num_out_links = /bits/ 8  <0x1>;
+					out_links = <0 &scaler_osd1_block>;
+				};
+				vpp_postblend_block: block@12 {
+					id = /bits/ 8  <VPP_POSTBLEND_BLOCK>;
+					block_name = "vpp_postblend_block";
+					type = /bits/ 8  <6>;
+					num_in_links = /bits/ 8  <0x2>;
+					in_links = <0 &scaler_osd1_block>,
+						<1 &osd_blend_block>;
+					num_out_links = <0x0>;
+				};
+			};
+		};
+
+		vpu_hw_para: vpu_hw_para@0 {
+			osd_ver = /bits/ 8 <0x2>;
+			afbc_type = /bits/ 8 <0x2>;
+			has_deband = /bits/ 8 <0x1>;
+			has_lut = /bits/ 8 <0x1>;
+			has_rdma = /bits/ 8 <0x1>;
+			osd_fifo_len = /bits/ 8 <64>;
+			vpp_fifo_len = /bits/ 32 <0xfff>;
+		};
+	};
+};

drivers/amlogic/drm/meson_lcd.c

@@ -411,6 +411,7 @@ static int am_lcd_get_modes(struct drm_panel *panel)
 	if (!lcd->mode)
 		return 0;
 
+	/*ToDo:the below is no use,may delete it!*/
 	mode = drm_mode_duplicate(drm, lcd->mode);
 	if (!mode)
 		return 0;
@@ -468,6 +469,7 @@ static void am_drm_lcd_display_mode_timing_init(struct am_drm_lcd_s *lcd)
 {
 	struct lcd_config_s *pconf;
 	unsigned short tmp;
+	char *vout_mode;
 
 	if (!lcd->lcd_drv) {
 		pr_info("invalid lcd driver\n");
@@ -477,10 +479,20 @@ static void am_drm_lcd_display_mode_timing_init(struct am_drm_lcd_s *lcd)
 	pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
 
 	pconf = lcd->lcd_drv->lcd_config;
+	vout_mode = get_vout_mode_internal();
 
 	lcd->mode = &am_lcd_mode;
 	lcd->timing = &am_lcd_timing;
 
+	if (vout_mode) {
+		strncpy(lcd->mode->name, vout_mode, DRM_DISPLAY_MODE_LEN);
+		lcd->mode->name[DRM_DISPLAY_MODE_LEN - 1] = 0;
+		/*ToDo:change it according to lcd drivers config*/
+		if (!strcmp(vout_mode, "panel"))
+			lcd->connector.connector_type = DRM_MODE_CONNECTOR_DSI;
+		else
+			lcd->connector.connector_type = DRM_MODE_CONNECTOR_LVDS;
+	}
 	lcd->mode->clock = pconf->lcd_timing.lcd_clk / 1000;
 	lcd->mode->hdisplay = pconf->lcd_basic.h_active;
 	tmp = pconf->lcd_basic.h_period - pconf->lcd_basic.h_active -
@@ -533,7 +545,7 @@ static void am_drm_lcd_display_mode_timing_init(struct am_drm_lcd_s *lcd)
 	lcd->timing->vsync_len.typ = pconf->lcd_timing.vsync_width;
 	lcd->timing->vsync_len.max = pconf->lcd_timing.vsync_width;
 
-	pr_info("am_drm_lcd: %s: lcd config:\n"
+	DRM_INFO("am_drm_lcd: %s: lcd config:\n"
 		"lcd_clk             %d\n"
 		"h_active            %d\n"
 		"v_active            %d\n"
@@ -549,7 +561,7 @@ static void am_drm_lcd_display_mode_timing_init(struct am_drm_lcd_s *lcd)
 		lcd->lcd_drv->lcd_config->lcd_basic.screen_height,
 		lcd->lcd_drv->lcd_config->lcd_timing.sync_duration_den,
 		lcd->lcd_drv->lcd_config->lcd_timing.sync_duration_num);
-	pr_info("am_drm_lcd: %s: display mode:\n"
+	DRM_INFO("am_drm_lcd: %s: display mode:\n"
 		"clock       %d\n"
 		"hdisplay    %d\n"
 		"vdisplay    %d\n"
@@ -563,7 +575,7 @@ static void am_drm_lcd_display_mode_timing_init(struct am_drm_lcd_s *lcd)
 		lcd->mode->width_mm,
 		lcd->mode->height_mm,
 		lcd->mode->vrefresh);
-	pr_info("am_drm_lcd: %s: timing:\n"
+	DRM_INFO("am_drm_lcd: %s: timing:\n"
 		"pixelclock   %d\n"
 		"hactive      %d\n"
 		"vactive      %d\n",
@@ -572,9 +584,33 @@ static void am_drm_lcd_display_mode_timing_init(struct am_drm_lcd_s *lcd)
 		lcd->timing->hactive.typ,
 		lcd->timing->vactive.typ);
 
-	pr_info("am_drm_lcd: %s %d\n", __func__, __LINE__);
+	DRM_INFO("am_drm_lcd: %s %d\n", __func__, __LINE__);
 }
 
+int am_drm_lcd_notify_callback(struct notifier_block *block, unsigned long cmd,
+	void *para)
+{
+	am_drm_lcd->lcd_drv = aml_lcd_get_driver();
+	if (!am_drm_lcd->lcd_drv) {
+		DRM_ERROR("invalid lcd driver, exit\n");
+		return -ENODEV;
+	}
+
+	switch (cmd) {
+	case VOUT_EVENT_MODE_CHANGE:
+		am_drm_lcd_display_mode_timing_init(am_drm_lcd);
+		DRM_INFO("%s:event MODE_CHANGE\n", __func__);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static struct notifier_block am_drm_lcd_notifier_nb = {
+	.notifier_call	= am_drm_lcd_notify_callback,
+};
+
 static const struct of_device_id am_meson_lcd_dt_ids[] = {
 	{ .compatible = "amlogic,drm-lcd", },
 	{},
@@ -600,8 +636,11 @@ static int am_meson_lcd_bind(struct device *dev, struct device *master,
 		pr_err("invalid lcd driver, exit\n");
 		return -ENODEV;
 	}
-
-	am_drm_lcd_display_mode_timing_init(am_drm_lcd);
+	/*
+	 * register vout client for timing init,
+	 * avoid init with null info when lcd probe with unifykey case.
+	 */
+	vout_register_client(&am_drm_lcd_notifier_nb);
 
 	drm_panel_init(&am_drm_lcd->panel);
 	am_drm_lcd->panel.dev = NULL;

drivers/amlogic/drm/meson_vpu.c

@@ -332,9 +332,12 @@ const struct meson_crtc_funcs meson_private_crtc_funcs = {
 char *am_meson_crtc_get_voutmode(struct drm_display_mode *mode)
 {
 	int i;
+	struct vinfo_s *vinfo;
 
-	if (!strcmp(mode->name, "panel"))
-		return "panel";
+	vinfo = get_current_vinfo();
+
+	if (vinfo && vinfo->mode == VMODE_LCD)
+		return mode->name;
 
 	for (i = 0; i < ARRAY_SIZE(am_vout_modes); i++) {
 		if (am_vout_modes[i].width == mode->hdisplay &&

drivers/amlogic/drm/meson_vpu_pipeline.c

@@ -31,7 +31,6 @@
 #define MAX_PORT_ID 32
 
 static struct meson_vpu_block **vpu_blocks;
-static int num_blocks;
 
 struct meson_vpu_link_para {
 	u8 id;
@@ -233,7 +232,7 @@ static void populate_block_link(void)
 	int i, j, id;
 	struct meson_vpu_block *mvb;
 
-	for (i = 0; i < num_blocks; i++) {
+	for (i = 0; i < BLOCK_ID_MAX; i++) {
 		mvb = vpu_blocks[i];
 
 		if (!mvb)
@@ -257,12 +256,13 @@ static int populate_vpu_pipeline(struct device_node *vpu_block_node,
 	struct device_node *child_node;
 	struct meson_vpu_block *mvb;
 	struct meson_vpu_block_para para;
+	u32 num_blocks;
 
 	num_blocks = of_get_child_count(vpu_block_node);
 	if (num_blocks <= 0)
 		return -ENODEV;
 
-	vpu_blocks = kcalloc(num_blocks, sizeof(*vpu_blocks), GFP_KERNEL);
+	vpu_blocks = kcalloc(BLOCK_ID_MAX, sizeof(*vpu_blocks), GFP_KERNEL);
 	if (!vpu_blocks)
 		return -ENOMEM;
 

drivers/amlogic/drm/meson_vpu_pipeline_traverse.c

@@ -57,19 +57,19 @@ static struct meson_vpu_block *neighbour(struct meson_vpu_block_state *mvbs,
 			continue;
 		next_state = meson_vpu_block_get_state(mvbl->link, state);
 		if (next_state->in_stack) {
-			//printk("%s already in stack.\n", mvbl->link->name);
+			DRM_DEBUG("%s already in stack.\n", mvbl->link->name);
 			continue;
 		}
 		if (!next_state->active) {
-			//printk("%s is not active.\n", mvbl->link->name);
+			DRM_DEBUG("%s is not active.\n", mvbl->link->name);
 			continue;
 		}
 		if (!mvbl->edges_active) {
-			//printk("edges is not active.\n");
+			DRM_DEBUG("edges is not active.\n");
 			continue;
 		}
 		if (mvbl->edges_visited) {
-			//printk("edges is already visited.\n");
+			DRM_DEBUG("edges is already visited.\n");
 			continue;
 		}
 
@@ -114,6 +114,8 @@ static void pipeline_dfs(int osd_index, struct meson_vpu_pipeline_state *mvps,
 	stack_push(mvs, start);
 	mvt->num_path = 0;
 	j = 0;
+	DRM_DEBUG("start->id=%d,name=%s\n", start->id, start->name);
+	DRM_DEBUG("end->id=%d,name=%s\n", end->id, end->name);
 
 	while (mvs->top) {
 		if (mvs->stack[mvs->top - 1] == end) {
@@ -133,12 +135,15 @@ static void pipeline_dfs(int osd_index, struct meson_vpu_pipeline_state *mvps,
 			next = neighbour(curr_state, &index, state);
 
 			if (next) {
+				DRM_DEBUG("next->id=%d,name=%s\n",
+					  next->id, next->name);
 				curr_state->outputs[index].edges_visited = 1;
 				next_state =
 					meson_vpu_block_get_state(next, state);
 				stack_push(mvs, next);
 				next_state->in_stack = 1;
 			} else {
+				DRM_DEBUG("next is NULL!!\n");
 				stack_pop(mvs);
 				curr_state->in_stack = 0;
 				pipeline_visit_clean(curr_state);

include/dt-bindings/display/meson-drm-ids.h

@@ -13,6 +13,7 @@
 #define OSD_BLEND_BLOCK 9
 #define OSD1_HDR_BLOCK 10
 #define VPP_POSTBLEND_BLOCK 11
+#define BLOCK_ID_MAX 12
 
 #define OSD1_PORT 0
 #define OSD2_PORT 1