Merge "ODROID-COMMON: hdmitx: Add 3440x1440p60hz display mode" into odroidg12-4.9.y

This commit is contained in:
Joy Cho
2020-09-11 08:27:56 +09:00
committed by Gerrit Code Review
6 changed files with 121 additions and 0 deletions

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@@ -1554,6 +1554,54 @@ static struct hdmi_format_para fmt_para_480x800p60_4x3 = {
},
};
static struct hdmi_format_para fmt_para_vesa_3440x1440p60_43x18 = {
.vic = HDMIV_3440x1440p60hz,
.name = "3440x1440p60hz",
.sname = "3440x1440p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
.tmds_clk_div40 = 0,
.tmds_clk = 319750,
.timing = {
.pixel_freq = 319750,
.frac_freq = 319750,
.h_freq = 88819,
.v_freq = 60000,
.vsync_polarity = 0, /* -VSync */
.hsync_polarity = 1, /* +HSync */
.h_active = 3440,
.h_total = 3600,
.h_blank = 160,
.h_front = 48,
.h_sync = 32,
.h_back = 80,
.v_active = 1440,
.v_total = 1481,
.v_blank = 41,
.v_front = 3,
.v_sync = 10,
.v_back = 28,
.v_sync_ln = 1,
},
.hdmitx_vinfo = {
.name = "3440x1440p60hz",
.mode = VMODE_HDMI,
.width = 3440,
.height = 1440,
.field_height = 1440,
.aspect_ratio_num = 43,
.aspect_ratio_den = 19,
.sync_duration_num = 60,
.sync_duration_den = 1,
.video_clk = 319750000,
.htotal = 3600,
.vtotal = 1481,
.viu_color_fmt = COLOR_FMT_YUV444,
.viu_mux = VIU_MUX_ENCP,
},
};
static struct hdmi_format_para fmt_para_custombuilt = {
.vic = HDMI_CUSTOMBUILT,
.name = "custombuilt",
@@ -2889,6 +2937,7 @@ static struct hdmi_format_para *all_fmt_paras[] = {
&fmt_para_vesa_2160x1200p90_9x5,
&fmt_para_vesa_2560x1600p60_8x5,
#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
&fmt_para_vesa_3440x1440p60_43x18,
&fmt_para_vesa_2560x1440p60_16x9,
&fmt_para_480x320p60_4x3,
&fmt_para_480x272p60_4x3,

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@@ -843,6 +843,17 @@ static struct hdmitx_vidpara hdmi_tx_video_params[] = {
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMIV_3440x1440p60hz,
.color_prefer = COLORSPACE_RGB444,
.color_depth = COLORDEPTH_24B,
.bar_info = B_BAR_VERT_HORIZ,
.repeat_time = NO_REPEAT,
.aspect_ratio = ASPECT_RATIO_SAME_AS_SOURCE,
.cc = CC_ITU709,
.ss = SS_SCAN_UNDER,
.sc = SC_SCALE_HORIZ_VERT,
},
{
.VIC = HDMI_CUSTOMBUILT,
.color_prefer = COLORSPACE_RGB444,

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@@ -1491,6 +1491,32 @@ static const struct reg_s tvregs_480x800p_60hz[] = {
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
};
static const struct reg_s tvregs_vesa_3440x1440p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 3599,},
{P_ENCP_VIDEO_MAX_LNCNT, 1480,},
{P_ENCP_VIDEO_HAVON_BEGIN, 80,},
{P_ENCP_VIDEO_HAVON_END, 3519,},
{P_ENCP_VIDEO_VAVON_BLINE, 28,},
{P_ENCP_VIDEO_VAVON_ELINE, 1467,},
{P_ENCP_VIDEO_HSO_BEGIN, 0,},
{P_ENCP_VIDEO_HSO_END, 32,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 10,},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0},
};
#endif
struct vic_tvregs_set {
@@ -1558,6 +1584,7 @@ static struct vic_tvregs_set tvregsTab[] = {
{HDMIV_2160x1200p90hz, tvregs_vesa_2160x1200p90hz},
{HDMIV_2560x1600p60hz, tvregs_vesa_2560x1600p60hz},
#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
{HDMIV_3440x1440p60hz, tvregs_vesa_3440x1440p60hz},
{HDMIV_2560x1440p60hz, tvregs_vesa_2560x1440p60hz},
{HDMI_480x320p60_4x3, tvregs_480x320p_60hz},
{HDMI_480x272p60_4x3, tvregs_480x272p_60hz},

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@@ -1722,6 +1722,22 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
TOTAL_FRAMES = 4;
break;
#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
case HDMIV_3440x1440p60hz:
INTERLACE_MODE = 0U;
PIXEL_REPEAT_VENC = 0;
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (3440*(1+PIXEL_REPEAT_HDMI));
ACTIVE_LINES = (1440/(1+INTERLACE_MODE));
LINES_F0 = 1481;
LINES_F1= 1481;
FRONT_PORCH = 48;
HSYNC_PIXELS = 32;
BACK_PORCH = 80;
EOF_LINES = 3;
VSYNC_LINES = 10;
SOF_LINES = 28;
TOTAL_FRAMES = 4;
break;
case HDMIV_2560x1600p60hz:
INTERLACE_MODE = 0U;
PIXEL_REPEAT_VENC = 0;

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@@ -821,6 +821,9 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
HDMI_VIC_END},
5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
{{HDMIV_3440x1440p60hz,
HDMI_VIC_END},
3197500, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
{{HDMIV_2560x1440p60hz,
HDMI_VIC_END},
4830000, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},

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@@ -349,6 +349,21 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
case 3197500:
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000485);
if (frac_rate)
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000110e1);
else
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
case 3960000:
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004a4);
if (frac_rate)