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Merge "ODROID-COMMON: hdmitx: Add 3440x1440p60hz display mode" into odroidg12-4.9.y
This commit is contained in:
@@ -1554,6 +1554,54 @@ static struct hdmi_format_para fmt_para_480x800p60_4x3 = {
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},
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};
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static struct hdmi_format_para fmt_para_vesa_3440x1440p60_43x18 = {
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.vic = HDMIV_3440x1440p60hz,
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.name = "3440x1440p60hz",
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.sname = "3440x1440p60hz",
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.pixel_repetition_factor = 0,
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.progress_mode = 1,
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.scrambler_en = 0,
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.tmds_clk_div40 = 0,
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.tmds_clk = 319750,
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.timing = {
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.pixel_freq = 319750,
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.frac_freq = 319750,
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.h_freq = 88819,
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.v_freq = 60000,
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.vsync_polarity = 0, /* -VSync */
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.hsync_polarity = 1, /* +HSync */
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.h_active = 3440,
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.h_total = 3600,
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.h_blank = 160,
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.h_front = 48,
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.h_sync = 32,
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.h_back = 80,
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.v_active = 1440,
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.v_total = 1481,
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.v_blank = 41,
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.v_front = 3,
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.v_sync = 10,
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.v_back = 28,
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.v_sync_ln = 1,
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},
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.hdmitx_vinfo = {
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.name = "3440x1440p60hz",
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.mode = VMODE_HDMI,
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.width = 3440,
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.height = 1440,
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.field_height = 1440,
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.aspect_ratio_num = 43,
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.aspect_ratio_den = 19,
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.sync_duration_num = 60,
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.sync_duration_den = 1,
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.video_clk = 319750000,
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.htotal = 3600,
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.vtotal = 1481,
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.viu_color_fmt = COLOR_FMT_YUV444,
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.viu_mux = VIU_MUX_ENCP,
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},
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};
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static struct hdmi_format_para fmt_para_custombuilt = {
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.vic = HDMI_CUSTOMBUILT,
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.name = "custombuilt",
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@@ -2889,6 +2937,7 @@ static struct hdmi_format_para *all_fmt_paras[] = {
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&fmt_para_vesa_2160x1200p90_9x5,
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&fmt_para_vesa_2560x1600p60_8x5,
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#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
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&fmt_para_vesa_3440x1440p60_43x18,
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&fmt_para_vesa_2560x1440p60_16x9,
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&fmt_para_480x320p60_4x3,
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&fmt_para_480x272p60_4x3,
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@@ -843,6 +843,17 @@ static struct hdmitx_vidpara hdmi_tx_video_params[] = {
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.ss = SS_SCAN_UNDER,
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.sc = SC_SCALE_HORIZ_VERT,
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},
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{
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.VIC = HDMIV_3440x1440p60hz,
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.color_prefer = COLORSPACE_RGB444,
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.color_depth = COLORDEPTH_24B,
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.bar_info = B_BAR_VERT_HORIZ,
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.repeat_time = NO_REPEAT,
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.aspect_ratio = ASPECT_RATIO_SAME_AS_SOURCE,
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.cc = CC_ITU709,
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.ss = SS_SCAN_UNDER,
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.sc = SC_SCALE_HORIZ_VERT,
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},
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{
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.VIC = HDMI_CUSTOMBUILT,
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.color_prefer = COLORSPACE_RGB444,
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@@ -1491,6 +1491,32 @@ static const struct reg_s tvregs_480x800p_60hz[] = {
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{P_ENCI_VIDEO_EN, 0},
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{MREG_END_MARKER, 0},
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};
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static const struct reg_s tvregs_vesa_3440x1440p60hz[] = {
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{P_VENC_VDAC_SETTING, 0xff,},
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{P_ENCP_VIDEO_EN, 0,},
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{P_ENCI_VIDEO_EN, 0,},
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{P_ENCP_VIDEO_MODE, 0x4040,},
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{P_ENCP_VIDEO_MODE_ADV, 0x18,},
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{P_ENCP_VIDEO_MAX_PXCNT, 3599,},
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{P_ENCP_VIDEO_MAX_LNCNT, 1480,},
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{P_ENCP_VIDEO_HAVON_BEGIN, 80,},
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{P_ENCP_VIDEO_HAVON_END, 3519,},
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{P_ENCP_VIDEO_VAVON_BLINE, 28,},
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{P_ENCP_VIDEO_VAVON_ELINE, 1467,},
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{P_ENCP_VIDEO_HSO_BEGIN, 0,},
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{P_ENCP_VIDEO_HSO_END, 32,},
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{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
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{P_ENCP_VIDEO_VSO_END, 0x32,},
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{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
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{P_ENCP_VIDEO_VSO_ELINE, 10,},
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{P_ENCP_VIDEO_EN, 1,},
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{P_ENCI_VIDEO_EN, 0,},
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{MREG_END_MARKER, 0},
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};
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#endif
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struct vic_tvregs_set {
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@@ -1558,6 +1584,7 @@ static struct vic_tvregs_set tvregsTab[] = {
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{HDMIV_2160x1200p90hz, tvregs_vesa_2160x1200p90hz},
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{HDMIV_2560x1600p60hz, tvregs_vesa_2560x1600p60hz},
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#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
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{HDMIV_3440x1440p60hz, tvregs_vesa_3440x1440p60hz},
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{HDMIV_2560x1440p60hz, tvregs_vesa_2560x1440p60hz},
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{HDMI_480x320p60_4x3, tvregs_480x320p_60hz},
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{HDMI_480x272p60_4x3, tvregs_480x272p_60hz},
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@@ -1722,6 +1722,22 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
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TOTAL_FRAMES = 4;
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break;
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#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
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case HDMIV_3440x1440p60hz:
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INTERLACE_MODE = 0U;
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PIXEL_REPEAT_VENC = 0;
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PIXEL_REPEAT_HDMI = 0;
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ACTIVE_PIXELS = (3440*(1+PIXEL_REPEAT_HDMI));
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ACTIVE_LINES = (1440/(1+INTERLACE_MODE));
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LINES_F0 = 1481;
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LINES_F1= 1481;
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FRONT_PORCH = 48;
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HSYNC_PIXELS = 32;
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BACK_PORCH = 80;
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EOF_LINES = 3;
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VSYNC_LINES = 10;
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SOF_LINES = 28;
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TOTAL_FRAMES = 4;
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break;
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case HDMIV_2560x1600p60hz:
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INTERLACE_MODE = 0U;
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PIXEL_REPEAT_VENC = 0;
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@@ -821,6 +821,9 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
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HDMI_VIC_END},
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5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
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#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
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{{HDMIV_3440x1440p60hz,
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HDMI_VIC_END},
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3197500, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
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{{HDMIV_2560x1440p60hz,
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HDMI_VIC_END},
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4830000, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
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@@ -349,6 +349,21 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
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pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
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break;
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#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
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case 3197500:
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hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000485);
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if (frac_rate)
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hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x000110e1);
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else
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hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
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hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
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hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
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hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
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hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
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hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
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hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
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WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
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pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
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break;
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case 3960000:
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hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004a4);
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if (frac_rate)
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