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drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
commit 022ac4c9c5 upstream.
1.Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2.we should show the current working clock freqency from clock table metric
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
fe0ec6f90e
commit
45bc323b81
@@ -184,6 +184,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
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uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
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DpmClocks_t *clk_table = smu->smu_table.clocks_table;
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SmuMetrics_t metrics;
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bool cur_value_match_level = false;
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if (!clk_table || clk_type >= SMU_CLK_COUNT)
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return -EINVAL;
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@@ -243,8 +244,13 @@ static int renoir_print_clk_levels(struct smu_context *smu,
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GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
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size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
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cur_value == value ? "*" : "");
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if (cur_value == value)
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cur_value_match_level = true;
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}
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if (!cur_value_match_level)
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size += sprintf(buf + size, " %uMhz *\n", cur_value);
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return size;
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}
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@@ -37,7 +37,7 @@ extern void renoir_set_ppt_funcs(struct smu_context *smu);
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freq = table->SocClocks[dpm_level].Freq; \
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break; \
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case SMU_MCLK: \
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freq = table->MemClocks[dpm_level].Freq; \
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freq = table->FClocks[dpm_level].Freq; \
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break; \
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case SMU_DCEFCLK: \
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freq = table->DcfClocks[dpm_level].Freq; \
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