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TD8801 : Add board td8801_v2

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This commit is contained in:
张昊
2011-11-21 21:15:26 +08:00
parent 13f630d8dd
commit 45ef5ba515
19 changed files with 7129 additions and 16 deletions
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2160
arch/arm/configs/rk29_td8801_v2_defconfig Normal file
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File diff suppressed because it is too large Load Diff

1
arch/arm/include/asm/hardware/gic.h
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@@ -36,6 +36,7 @@
extern void __iomem *gic_cpu_base_addr;
extern struct irq_chip gic_arch_extn;
#define grf_readl(offset) readl(RK29_GRF_BASE + offset)
void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);

6
arch/arm/mach-rk29/Kconfig
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@@ -53,6 +53,12 @@ config MACH_RK29_A22
help
Support for the ROCKCHIP Board For A22.
config MACH_RK29_TD8801_V2
depends on ARCH_RK29
bool "ROCKCHIP Board Rk29 For TD8801_v2"
help
Support for the ROCKCHIP Board For TD8801_v2.
config MACH_RK29_PHONEPADSDK
depends on ARCH_RK29
bool "ROCKCHIP Board Rk29 For Phone Pad Sdk"

1
arch/arm/mach-rk29/Makefile
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@@ -21,6 +21,7 @@ obj-$(CONFIG_MACH_RK29_MALATA) += board-malata.o board-rk29malata-key.o board-rk
obj-$(CONFIG_MACH_RK29_PHONESDK) += board-rk29-phonesdk.o board-rk29-phonesdk-key.o board-rk29-phonesdk-rfkill.o
obj-$(CONFIG_MACH_RK29FIH) += board-rk29-fih.o board-rk29-fih-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o
obj-$(CONFIG_MACH_RK29_A22) += board-rk29-a22.o board-rk29-a22-key.o board-rk29-a22-rfkill.o
obj-$(CONFIG_MACH_RK29_TD8801_V2) += board-rk29-td8801_v2.o board-rk29-td8801_v2-key.o board-rk29-td8801_v2-rfkill.o
obj-$(CONFIG_MACH_RK29_PHONEPADSDK) += board-rk29phonepadsdk.o board-rk29phonepadsdk-key.o board-rk29phonepadsdk-rfkill.o board-rk29phonepadsdk-power.o
obj-$(CONFIG_MACH_RK29_newton) += board-rk29-newton.o board-rk29-newton-key.o board-newton-rfkill.o board-rk29sdk-power.o
obj-$(CONFIG_MACH_RK29_K97) += board-rk29-k97.o board-rk29k97-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o

2
arch/arm/mach-rk29/board-rk29-phonesdk.c
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@@ -2623,7 +2623,9 @@ struct rk29_sdmmc_platform_data default_sdmmc1_data = {
MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
.io_init = rk29_sdmmc1_cfg_gpio,
.dma_name = "sdio",
#if !defined(CONFIG_SDMMC_RK29_OLD)
.set_iomux = rk29_sdmmc_set_iomux,
#endif
#ifdef CONFIG_SDMMC1_USE_DMA
.use_dma = 1,
#else

105
arch/arm/mach-rk29/board-rk29-td8801_v2-key.c Normal file
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@@ -0,0 +1,105 @@
#include <mach/key.h>
#include <mach/gpio.h>
#define EV_ENCALL KEY_F4
#define EV_MENU KEY_F1
#define PRESS_LEV_LOW 1
#define PRESS_LEV_HIGH 0
static struct rk29_keys_button key_button[] = {
{
.desc = "menu",
.code = EV_MENU,
.gpio = RK29_PIN6_PA0,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol+",
.code = KEY_VOLUMEUP,
.gpio = RK29_PIN6_PA1,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol-",
.code = KEY_VOLUMEDOWN,
.gpio = RK29_PIN6_PA2,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "home",
.code = KEY_HOME,
.gpio = RK29_PIN6_PA3,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "search",
.code = KEY_SEARCH,
.gpio = RK29_PIN6_PA4,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "esc",
.code = KEY_BACK,
.gpio = RK29_PIN6_PA5,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "sensor",
.code = KEY_CAMERA,
.gpio = RK29_PIN6_PA6,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "play",
.code = KEY_POWER,
.gpio = RK29_PIN6_PA7,
.active_low = PRESS_LEV_LOW,
.wakeup = 1,
},
#if 0
{
.desc = "vol+",
.code = KEY_VOLUMEDOWN,
.adc_value = 95,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol-",
.code = KEY_VOLUMEUP,
.adc_value = 249,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "menu",
.code = EV_MENU,
.adc_value = 406,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "home",
.code = KEY_HOME,
.code_long_press = KEY_F4,
.adc_value = 561,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "esc",
.code = KEY_ESC,
.adc_value = 726,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "adkey6",
.code = KEY_BACK,
.code_long_press = EV_ENCALL,
.adc_value = 899,
.active_low = PRESS_LEV_LOW,
},
#endif
};
struct rk29_keys_platform_data rk29_keys_pdata = {
.buttons = key_button,
.nbuttons = ARRAY_SIZE(key_button),
.chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
};

313
arch/arm/mach-rk29/board-rk29-td8801_v2-rfkill.c Normal file
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@@ -0,0 +1,313 @@
/*
* Copyright (C) 2010 ROCKCHIP, Inc.
* Author: roger_chen <cz@rock-chips.com>
*
* This program is the bluetooth device bcm4329's driver,
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/rfkill.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/wakelock.h>
#include <linux/fs.h>
#include <asm/uaccess.h>
#include <mach/gpio.h>
#include <asm/irq.h>
#include <mach/iomux.h>
#include <linux/wakelock.h>
#include <linux/timer.h>
#include <mach/board.h>
#if 0
#define DBG(x...) printk(KERN_INFO x)
#else
#define DBG(x...)
#endif
#define BT_WAKE_HOST_SUPPORT 1
struct bt_ctrl
{
struct rfkill *bt_rfk;
#if BT_WAKE_HOST_SUPPORT
struct timer_list tl;
bool b_HostWake;
struct wake_lock bt_wakelock;
#endif
};
#define BT_GPIO_POWER RK29_PIN5_PD6
#define IOMUX_BT_GPIO_POWER rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
#define BT_GPIO_RESET RK29_PIN6_PC7
#define BT_GPIO_WAKE_UP RK29_PIN6_PD0
#define BT_GPIO_WAKE_UP_HOST RK29_PIN4_PD4
#define IOMUX_BT_GPIO_WAKE_UP_HOST() rk29_mux_api_set(GPIO4D4_CPUTRACECLK_NAME,GPIO4H_GPIO4D4);
//bt cts paired to uart rts
#define UART_RTS RK29_PIN2_PA7
#define IOMUX_UART_RTS_GPIO rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_GPIO2A7);
#define IOMUX_UART_RTS rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
#define BT_WAKE_LOCK_TIMEOUT 10 //s
static const char bt_name[] = "bcm4329";
extern int rk29sdk_bt_power_state;
extern int rk29sdk_wifi_power_state;
struct bt_ctrl gBtCtrl;
#if BT_WAKE_HOST_SUPPORT
void resetBtHostSleepTimer(void)
{
mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ó<EFBFBD>ʱֵ<CAB1><D6B5>
}
void btWakeupHostLock(void)
{
if(gBtCtrl.b_HostWake == false){
DBG("*************************Lock\n");
wake_lock(&(gBtCtrl.bt_wakelock));
gBtCtrl.b_HostWake = true;
}
}
void btWakeupHostUnlock(void)
{
if(gBtCtrl.b_HostWake == true){
DBG("*************************UnLock\n");
wake_unlock(&(gBtCtrl.bt_wakelock)); //<2F><>ϵͳ˯<CDB3><CBAF>
gBtCtrl.b_HostWake = false;
}
}
static void timer_hostSleep(unsigned long arg)
{
DBG("%s---b_HostWake=%d\n",__FUNCTION__,gBtCtrl.b_HostWake);
btWakeupHostUnlock();
}
#ifdef CONFIG_PM
static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
{
DBG("%s\n",__FUNCTION__);
//To prevent uart to receive bt data when suspended
IOMUX_UART_RTS_GPIO;
gpio_request(UART_RTS, "uart_rts");
gpio_direction_output(UART_RTS, 0);
gpio_set_value(UART_RTS, GPIO_HIGH);
return 0;
}
static int bcm4329_rfkill_resume(struct platform_device *pdev)
{
DBG("%s\n",__FUNCTION__);
btWakeupHostLock();
resetBtHostSleepTimer();
gpio_set_value(UART_RTS, GPIO_LOW);
IOMUX_UART_RTS;
return 0;
}
#else
#define bcm4329_rfkill_suspend NULL
#define bcm4329_rfkill_resume NULL
#endif
static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
{
DBG("%s\n",__FUNCTION__);
btWakeupHostLock();
resetBtHostSleepTimer();
return IRQ_HANDLED;
}
#endif
#ifdef CONFIG_BT_HCIBCM4325
int bcm4325_sleep(int bSleep)
{
// printk("*************bt enter sleep***************\n");
if (bSleep)
gpio_set_value(BT_GPIO_WAKE_UP, GPIO_LOW); //low represent bt device may enter sleep
else
gpio_set_value(BT_GPIO_WAKE_UP, GPIO_HIGH); //high represent bt device must be awake
//printk("sleep=%d\n",bSleep);
}
#endif
static int bcm4329_set_block(void *data, bool blocked)
{
DBG("%s---blocked :%d\n", __FUNCTION__, blocked);
IOMUX_BT_GPIO_POWER;
if (false == blocked) {
gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
mdelay(200);
gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
mdelay(200);
#if BT_WAKE_HOST_SUPPORT
btWakeupHostLock();
#endif
pr_info("bt turn on power\n");
}
else {
#if BT_WAKE_HOST_SUPPORT
btWakeupHostUnlock();
#endif
if (!rk29sdk_wifi_power_state) {
gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
mdelay(20);
pr_info("bt shut off power\n");
}else {
pr_info("bt shouldn't shut off power, wifi is using it!\n");
}
gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
mdelay(20);
}
rk29sdk_bt_power_state = !blocked;
return 0;
}
static const struct rfkill_ops bcm4329_rfk_ops = {
.set_block = bcm4329_set_block,
};
static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
{
int rc = 0;
bool default_state = true;
DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
/* default to bluetooth off */
bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
NULL,
RFKILL_TYPE_BLUETOOTH,
&bcm4329_rfk_ops,
NULL);
if (!gBtCtrl.bt_rfk)
{
printk("fail to rfkill_allocate************\n");
return -ENOMEM;
}
rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
rc = rfkill_register(gBtCtrl.bt_rfk);
if (rc)
{
printk("failed to rfkill_register,rc=0x%x\n",rc);
rfkill_destroy(gBtCtrl.bt_rfk);
}
gpio_request(BT_GPIO_POWER, NULL);
gpio_request(BT_GPIO_RESET, NULL);
gpio_request(BT_GPIO_WAKE_UP, NULL);
#if BT_WAKE_HOST_SUPPORT
init_timer(&(gBtCtrl.tl));
gBtCtrl.tl.expires = jiffies + BT_WAKE_LOCK_TIMEOUT*HZ;
gBtCtrl.tl.function = timer_hostSleep;
add_timer(&(gBtCtrl.tl));
gBtCtrl.b_HostWake = false;
wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
if (rc) {
printk("%s:failed to request RAHO_BT_WAKE_UP_HOST\n",__FUNCTION__);
}
IOMUX_BT_GPIO_WAKE_UP_HOST();
gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
rc = request_irq(gpio_to_irq(BT_GPIO_WAKE_UP_HOST),bcm4329_wake_host_irq,IRQF_TRIGGER_FALLING,NULL,NULL);
if(rc)
{
printk("%s:failed to request RAHO_BT_WAKE_UP_HOST irq\n",__FUNCTION__);
gpio_free(BT_GPIO_WAKE_UP_HOST);
}
enable_irq_wake(gpio_to_irq(BT_GPIO_WAKE_UP_HOST)); // so RAHO_BT_WAKE_UP_HOST can wake up system
printk(KERN_INFO "bcm4329 module has been initialized,rc=0x%x\n",rc);
#endif
return rc;
}
static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
{
if (gBtCtrl.bt_rfk)
rfkill_unregister(gBtCtrl.bt_rfk);
gBtCtrl.bt_rfk = NULL;
#if BT_WAKE_HOST_SUPPORT
del_timer(&(gBtCtrl.tl));//ɾ<><C9BE><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
btWakeupHostUnlock();
wake_lock_destroy(&(gBtCtrl.bt_wakelock));
#endif
platform_set_drvdata(pdev, NULL);
DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
return 0;
}
static struct platform_driver bcm4329_rfkill_driver = {
.probe = bcm4329_rfkill_probe,
.remove = __devexit_p(bcm4329_rfkill_remove),
.driver = {
.name = "rk29sdk_rfkill",
.owner = THIS_MODULE,
},
#if BT_WAKE_HOST_SUPPORT
.suspend = bcm4329_rfkill_suspend,
.resume = bcm4329_rfkill_resume,
#endif
};
/*
* Module initialization
*/
static int __init bcm4329_mod_init(void)
{
int ret;
DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
ret = platform_driver_register(&bcm4329_rfkill_driver);
printk("ret=0x%x\n", ret);
return ret;
}
static void __exit bcm4329_mod_exit(void)
{
platform_driver_unregister(&bcm4329_rfkill_driver);
}
module_init(bcm4329_mod_init);
module_exit(bcm4329_mod_exit);
MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
MODULE_AUTHOR("roger_chen cz@rock-chips.com");
MODULE_LICENSE("GPL");

3693
arch/arm/mach-rk29/board-rk29-td8801_v2.c Executable file
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File diff suppressed because it is too large Load Diff

10
arch/arm/mach-rk29/devices.c
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@@ -221,6 +221,16 @@ struct platform_device rk29_device_backlight = {
}
};
#endif
#ifdef CONFIG_BUTTON_LIGHT
struct platform_device rk29_device_buttonlight = {
.name = "rk29_button_light",
.id = -1,
.dev = {
.platform_data = &rk29_button_light_info,
}
};
#endif
#ifdef CONFIG_SDMMC0_RK29
#ifndef CONFIG_EMMC_RK29
static struct resource resources_sdmmc0[] = {

2
arch/arm/mach-rk29/devices.h
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@@ -65,7 +65,9 @@ extern struct platform_device rk29_device_sdmmc1;
extern struct platform_device rk29_device_adc;
extern struct platform_device rk29_device_vmac;
extern struct rk29_bl_info rk29_bl_info;
extern struct rk29_button_light_info rk29_button_light_info;
extern struct platform_device rk29_device_backlight;
extern struct platform_device rk29_device_buttonlight;
extern struct platform_device rk29_device_usb20_otg;
extern struct platform_device rk29_device_usb20_host;
extern struct platform_device rk29_device_usb11_host;

522
arch/arm/mach-rk29/i2c_sram.c Executable file
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@@ -0,0 +1,522 @@
#include <mach/rk29_iomap.h>
#include <mach/board.h>
#include <mach/sram.h>
#include <mach/iomux.h>
#include <mach/cru.h>
#include <asm/io.h>
#include <mach/gpio.h>
#if defined(CONFIG_RK29_I2C_INSRAM)
#define I2C_SPEED 200
#if defined(CONFIG_MACH_RK29_TD8801_V2)
/******************need set when you use i2c*************************/
#define I2C_SADDR (0x34) /* slave address ,wm8310 addr is 0x34*/
#define SRAM_I2C_CH 1 //CH==0, i2c0,CH==1, i2c1,CH==2, i2c2,CH==3, i2c3
#define SRAM_I2C_ADDRBASE RK29_I2C1_BASE //RK29_I2C0_BASE\RK29_I2C2_BASE\RK29_I2C3_BASE
#define I2C_SLAVE_ADDR_LEN 1 // 2:slav addr is 10bit ,1:slav addr is 7bit
#define I2C_SLAVE_REG_LEN 2 // 2:slav reg addr is 16 bit ,1:is 8 bit
#define SRAM_I2C_DATA_BYTE 2 //i2c transmission data is 1bit(8wei) or 2bit(16wei)
#define GRF_GPIO_IOMUX GRF_GPIO1L_IOMUX
/*ch=0:GRF_GPIO2L_IOMUX,ch=1:GRF_GPIO1L_IOMUX,ch=2:GRF_GPIO5H_IOMUX,ch=3:GRF_GPIO2L_IOMUX*/
#define I2C_GRF_GPIO_IOMUX (~(0x03<<14))&(~(0x03<<12))|(0x01<<14)|(0x01<<12)
/*CH=0:(~(0x03<<30))&(~(0x03<<28))|(0x01<<30)|(0x01<<28),CH=1:(~(0x03<<14))&(~(0x03<<12))|(0x01<<14)|(0x01<<12),
CH=2:(~(0x03<<24))&(~(0x03<<22))|(0x01<<24)|(0x01<<22),CH=3:(~(0x03<<26))&(~(0x03<<24))|(0x02<<26)|(0x02<<24)*/
/***************************************/
#if defined(SRAM_I2C_CH)
#define CRU_CLKGATE_ADDR CRU_CLKGATE2_CON
#define CRU_CLKGATE_BIT SRAM_I2C_CH+11
#else
#define CRU_CLKGATE_ADDR CRU_CLKGATE0_CON
#define CRU_CLKGATE_BIT 26
#endif
//#define SRAM_I2C_ADDRBASE (RK29_I2C##SRAM_I2C_CH##_BASE )
#define I2C_SLAVE_TYPE (((I2C_SLAVE_ADDR_LEN-1)<<4)|((I2C_SLAVE_REG_LEN-1)))
#define uint8 unsigned char
#define uint16 unsigned short
#define uint32 unsigned int
uint32 __sramdata data[5];
#define CRU_CLKGATE0_CON 0x54
#define CRU_CLKGATE2_CON 0x64
#define CRU_CLKGATE1_CON 0x60
#define CRU_CLKSEL0_CON 0x14
#define GRF_GPIO5H_IOMUX 0x74
#define GRF_GPIO2L_IOMUX 0x58
#define GRF_GPIO1L_IOMUX 0x50
#define I2C_ARBITR_LOSE_STATUS (1<<7) // Arbitration lose STATUS
#define I2C_RECE_INT_MACKP (1<<1) // Master ACK period interrupt status bit
#define I2C_RECE_INT_MACK (1) // Master receives ACK interrupt status bit
#define I2C_MTXR (0x0000) /* master transmit */
#define I2C_MRXR (0x0004) /* master receive */
#define I2C_IER (0x0014) /* interrupt enable control */
#define I2C_ISR (0x0018) /* interrupt status, write 0 to clear */
#define I2C_LCMR (0x001c) /* stop/start/resume command, write 1 to set */
#define I2C_LSR (0x0020) /* i2c core status */
#define I2C_CONR (0x0024) /* i2c config */
#define I2C_OPR (0x0028) /* i2c core config */
#define I2C_MASTER_TRAN_MODE (1<<3)
#define I2C_MASTER_PORT_ENABLE (1<<2)
#define I2C_CON_NACK (1 << 4)
#define I2C_CON_ACK (0)
#define I2C_LCMR_RESUME (1<<2)
#define I2C_LCMR_STOP (1<<1)
#define I2C_LCMR_START (1<<0)
#define SRAM_I2C_WRITE (0x0ul)
#define SRAM_I2C_READ (0x1ul)
#define I2C_MASTER_RECE_MODE (0)
#define I2C_CORE_ENABLE (1<<6)
#define I2C_CORE_DISABLE (0)
#define SRAM_I2C_CLK_ENABLE() writel((~0x000000085), RK29_CRU_BASE + CRU_CLKGATE1_CON);
#define SRAM_I2C_CLK_DISABLE() writel(~0, RK29_CRU_BASE + CRU_CLKGATE1_CON);
#define sram_i2c_set_mode() do{ writel(0x0,SRAM_I2C_ADDRBASE + I2C_ISR);writel(0x0, SRAM_I2C_ADDRBASE + I2C_IER);writel((readl(SRAM_I2C_ADDRBASE + I2C_CONR)&(~(0x1ul<<4)))|I2C_MASTER_TRAN_MODE|I2C_MASTER_PORT_ENABLE, SRAM_I2C_ADDRBASE + I2C_CONR);}while(0)
void __sramfunc sram_i2c_start(void);
void __sramfunc sram_i2c_stop(void);
uint8 __sramfunc sram_i2c_wait_event(void);
uint8 __sramfunc sram_i2c_send_data(uint8 buf, uint8 startbit);
uint8 __sramfunc sram_i2c_read_data(uint8 *buf);
uint8 __sramfunc sram_i2c_slaveAdr(uint16 I2CSlaveAddr, uint8 addressBit, uint8 read_or_write);
void __sramfunc sram_printch(char byte);
void __sramfunc print_Hex(unsigned int hex);
void i2c_interface_ctr_reg_pread()
{
readl(SRAM_I2C_ADDRBASE);
readl(RK29_CRU_BASE);
readl(RK29_GRF_BASE);
readl(RK29_GPIO0_BASE);
readl(RK29_GPIO1_BASE);
readl(RK29_GPIO2_BASE);
readl(RK29_GPIO3_BASE);
readl(RK29_GPIO4_BASE);
readl(RK29_GPIO5_BASE);
readl(RK29_GPIO6_BASE);
}
void __sramfunc sram_i2c_delay(int delay_time)
{
int n = 100 * delay_time;
while(n--)
{
__asm__ __volatile__("");
}
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_init
Desc : initialize the necessary registers
Params : channel-determine which I2C bus we used
Return : none
------------------------------------------------------------------------------------------------------*/
void __sramfunc sram_i2c_init()
{
//enable cru_clkgate1 clock
data[0] = readl(RK29_CRU_BASE + CRU_CLKGATE1_CON);
writel(data[0]&(~0x00000085), RK29_CRU_BASE + CRU_CLKGATE1_CON);
//set the pclk
data[1] = readl(RK29_CRU_BASE + CRU_CLKSEL0_CON);
writel(data[1]&(~(0x07 << 5))&(~(0x03 << 10)) | (0x03 << 10), RK29_CRU_BASE + CRU_CLKSEL0_CON);
data[2] = readl(RK29_CRU_BASE + CRU_CLKGATE_ADDR);
writel(data[2]&(~(0x01 << CRU_CLKGATE_BIT)), RK29_CRU_BASE + CRU_CLKGATE_ADDR);
data[3] = readl(RK29_GRF_BASE + GRF_GPIO_IOMUX);
writel(data[3]&I2C_GRF_GPIO_IOMUX, RK29_GRF_BASE + GRF_GPIO_IOMUX);
//reset I2c-reg base
data[4] = readl(SRAM_I2C_ADDRBASE + I2C_OPR);
writel(data[4] | (0x1ul << 7), SRAM_I2C_ADDRBASE + I2C_OPR);
sram_i2c_delay(10);
writel(data[4]&(~(0x1ul << 7)), SRAM_I2C_ADDRBASE + I2C_OPR);
writel(0x0, SRAM_I2C_ADDRBASE + I2C_LCMR);
//disable arq
writel(0x0, SRAM_I2C_ADDRBASE + I2C_IER);
writel(data[4]&(~0x03f), SRAM_I2C_ADDRBASE + I2C_OPR);
//enable i2c core
writel(data[4] | I2C_CORE_ENABLE , SRAM_I2C_ADDRBASE + I2C_OPR);
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_deinit
Desc : de-initialize the necessary registers
Params : noe
Return : none
------------------------------------------------------------------------------------------------------*/
void __sramfunc sram_i2c_deinit(void)
{
SRAM_I2C_CLK_ENABLE();
//restore i2c opr reg
writel(data[4], SRAM_I2C_ADDRBASE + I2C_OPR);
//restore iomux reg
writel(data[3], RK29_GRF_BASE + GRF_GPIO_IOMUX);
//restore cru gate2
writel(data[2], RK29_CRU_BASE + CRU_CLKGATE_ADDR);
//restore scu clock reg
writel(data[1], RK29_CRU_BASE + CRU_CLKSEL0_CON);
//restore cru gate1
writel(data[0], RK29_CRU_BASE + CRU_CLKGATE1_CON);
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_start
Desc : start i2c
Params : none
Return : none
------------------------------------------------------------------------------------------------------*/
void __sramfunc sram_i2c_start(void)
{
writel(I2C_LCMR_START | I2C_LCMR_RESUME, SRAM_I2C_ADDRBASE + I2C_LCMR);
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_stop
Desc : stop i2c
Params : none
Return : none
------------------------------------------------------------------------------------------------------*/
void __sramfunc sram_i2c_stop(void)
{
writel(I2C_LCMR_STOP | I2C_LCMR_RESUME, SRAM_I2C_ADDRBASE + I2C_LCMR);
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_wait_event
Desc : wait the ack
Params : none
Return : success: return 0; fail: return 1
------------------------------------------------------------------------------------------------------*/
uint8 __sramfunc sram_i2c_wait_event(void)
{
unsigned int isr, waiteSendDelay = 3;
isr = readl(SRAM_I2C_ADDRBASE + I2C_ISR);
while (waiteSendDelay > 0)
{
if ((isr & I2C_ARBITR_LOSE_STATUS) != 0)
{
writel(0x0, SRAM_I2C_ADDRBASE + I2C_ISR);
return 1;
}
if ((isr & I2C_RECE_INT_MACK) != 0)
{
break;
}
sram_i2c_delay(1);
waiteSendDelay--;
}
writel(isr & (~0x1ul) , SRAM_I2C_ADDRBASE + I2C_ISR);
return 0;
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_send_data
Desc : send a byte data
Params : buf: the data we need to send;
startbit: startbit=1, send a start signal
startbit=0, do not send a start signal
Return : success: return 0; fail: return 1
------------------------------------------------------------------------------------------------------*/
uint8 __sramfunc sram_i2c_send_data(uint8 buf, uint8 startbit)
{
writel(buf, SRAM_I2C_ADDRBASE + I2C_MTXR);
readl(SRAM_I2C_ADDRBASE + I2C_LCMR);
if(startbit)
{
writel(I2C_LCMR_START | I2C_LCMR_RESUME, SRAM_I2C_ADDRBASE + I2C_LCMR);
sram_i2c_delay(50);
}
else
{
writel(I2C_LCMR_RESUME, SRAM_I2C_ADDRBASE + I2C_LCMR);
sram_i2c_delay(50);
}
if(sram_i2c_wait_event() != 0)
return 1;
return 0;
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_send_data
Desc : receive a byte data
Params : buf: save the data we received
Return : success: return 0; fail: return 1
------------------------------------------------------------------------------------------------------*/
uint8 __sramfunc sram_i2c_read_data(uint8 *buf)
{
unsigned int ret;
uint8 waitDelay = 3;
ret = readl(SRAM_I2C_ADDRBASE + I2C_LCMR);
writel(ret | I2C_LCMR_RESUME, SRAM_I2C_ADDRBASE + I2C_LCMR);
while(waitDelay > 0)
{
ret = readl(SRAM_I2C_ADDRBASE + I2C_ISR);
if((ret & I2C_ARBITR_LOSE_STATUS) != 0)
return 1;
if((ret & I2C_RECE_INT_MACKP) != 0)
break;
waitDelay--;
}
sram_i2c_delay(50);
*buf = (uint8)readl(SRAM_I2C_ADDRBASE + I2C_MRXR);
ret = readl(SRAM_I2C_ADDRBASE + I2C_ISR);
writel(ret & (~(0x1 << 1)), SRAM_I2C_ADDRBASE + I2C_ISR);
return 0;
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_slaveAdr
Desc : send the slaveAddr in 10bit mode or in 7bit mode
Params : I2CSlaveAddr: slave address
addressbit: high 4bits determine 7 bits or 10 bits slave address锛沴ow 4bits determine 8 bits or 16 bits regAddress
high 4bits==7, slave address is 7 bits
high 4bits==10,slave address is 10 bits
low 4bits==0, slave address is 8 bits
low 4bits==1, slave address is 16 bits
read_or_write: read a data or write a data from salve
Return : sucess return 0, fail return 0
------------------------------------------------------------------------------------------------------*/
uint8 __sramfunc sram_i2c_slaveAdr(uint16 I2CSlaveAddr, uint8 addressBit, uint8 read_or_write)
{
uint8 retv = 1;
if((addressBit & 0xf0) == 0x10) //10bit slave address
{
if(sram_i2c_send_data((I2CSlaveAddr >> 7) & 0x06 | 0xf0 | read_or_write, 1) != 0)
goto STOP;
sram_i2c_delay(50);
if(sram_i2c_send_data((I2CSlaveAddr) & 0xff | read_or_write, 0) != 0)
goto STOP;
}
else //7bit slave address
{
if(sram_i2c_send_data((I2CSlaveAddr << 1) | read_or_write, 1) != 0)
goto STOP;
}
retv = 0;
STOP:
//sram_i2c_stop();
return retv;
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_wirte
Desc : conduct wirte operation
Params : I2CSlaveAddr: slave address
regAddr: slave register address
*pdataBuff: data we want to write
size: number of bytes
addressbit: high 4bits determine 7 bits or 10 bits slave address锛沴ow 4bits determine 8 bits or 16 bits regAddress
high 4bits==7, slave address is 7 bits
high 4bits==10,slave address is 10 bits
low 4bits==0, slave address is 8 bits
low 4bits==1, slave address is 16 bits
Return : success: return 0; fail: return 1
------------------------------------------------------------------------------------------------------*/
uint8 __sramfunc sram_i2c_write(uint16 I2CSlaveAddr, uint16 regAddr, void *pdataBuff, uint16 size, uint8 addressBit)
{
unsigned int ret;
uint8 *pdata;
uint8 bit_if16 = (addressBit & 0x0f) ? 0x2 : 0x1;
uint8 retv = 1;
pdata = (uint8 *) pdataBuff;
sram_i2c_set_mode();
sram_i2c_delay(50);
if((retv = sram_i2c_slaveAdr(I2CSlaveAddr, addressBit, SRAM_I2C_WRITE)) != 0)
goto STOP;
sram_i2c_delay(50);
do
{
bit_if16--;
if (sram_i2c_send_data((regAddr >> (bit_if16 ? 8 : 0)) & 0xff, 0) != 0)
goto STOP;
}
while(bit_if16);
sram_i2c_delay(50);
do
{
if (sram_i2c_send_data(*pdata, 0) != 0)
goto STOP;
sram_i2c_delay(50);
pdata++;
size--;
}
while (size);
retv = 0;
ret = readl( SRAM_I2C_ADDRBASE + I2C_CONR);
writel(ret | I2C_CON_NACK, SRAM_I2C_ADDRBASE + I2C_CONR);
STOP:
sram_i2c_stop();
return retv;
}
/*-------------------------------------------------------------------------------------------------------
Name : sram_i2c_read
Desc : conduct read operation
Params : I2CSlaveAddr: slave address
regAddr: slave register address
*pdataBuff: save the data master received
size: number of bytes
addressbit: high 4bits determine 7 bits or 10 bits slave address锛沴ow 4bits determine 8 bits or 16 bits regAddress
high 4bits==7, slave address is 7 bits
high 4bits==10,slave address is 10 bits
low 4bits==0, slave address is 8 bits
low 4bits==1, slave address is 16 bits
mode: mode=0, NORMALMODE
mode=1, DIRECTMODE
Return : success: return 0; fail: return 1
------------------------------------------------------------------------------------------------------*/
uint8 __sramfunc sram_i2c_read(uint16 I2CSlaveAddr, uint16 regAddr, void *pdataBuff, uint16 size, uint8 addressBit)
{
uint8 *pdata;
unsigned int ret;
uint8 bit_if16 = (addressBit & 0x0f) ? 0x2 : 0x1;
uint8 retv = 1;
pdata = (uint8 *)pdataBuff;
sram_i2c_set_mode();
//sram_i2c_delay(50);
if((retv = sram_i2c_slaveAdr(I2CSlaveAddr, addressBit, SRAM_I2C_WRITE)) != 0)
goto STOP;
//sram_i2c_delay(50);
do
{
bit_if16--;
if (sram_i2c_send_data((regAddr >> (bit_if16 ? 8 : 0)) & 0xff, 0) != 0)
goto STOP;
}
while(bit_if16);
sram_i2c_delay(50);
if((retv = sram_i2c_slaveAdr(I2CSlaveAddr, addressBit, SRAM_I2C_READ)) != 0)
goto STOP;
writel((ret&(~(0x1 << 3))) | I2C_MASTER_RECE_MODE | I2C_MASTER_PORT_ENABLE, SRAM_I2C_ADDRBASE + I2C_CONR);
do
{
ret = readl(SRAM_I2C_ADDRBASE + I2C_CONR);
if(size == 1)
{
if((sram_i2c_read_data(pdata)) != 0)
goto STOP;
writel(ret | I2C_CON_NACK, SRAM_I2C_ADDRBASE + I2C_CONR);
}
else
{
if((sram_i2c_read_data(pdata)) != 0)
goto STOP;
writel(ret & (~(0x1ul << 4)) | I2C_CON_ACK, SRAM_I2C_ADDRBASE + I2C_CONR);
}
//sram_i2c_delay(50);
pdata++;
size--;
}
while (size);
retv = 0;
STOP:
sram_i2c_stop();
return retv;
}
unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol)
{
uint8 slaveaddr;
uint16 slavereg;
unsigned int ret, mask, addr;
uint8 data[2];
sram_i2c_init(); //init i2c device
slaveaddr = I2C_SADDR; //slave device addr
slavereg = 0x4003; // reg addr
data[0] = 0x00; //clear i2c when read
data[1] = 0x00;
ret = sram_i2c_read(slaveaddr, slavereg, data, SRAM_I2C_DATA_BYTE, I2C_SLAVE_TYPE);
// print_Hex(data[0]); //read data saved in data
// print_Hex(data[1]); //read data saved in data
//sram_printch('\n');
data[0] |= (0x1<<6); //write data
sram_i2c_write(slaveaddr, slavereg, data, SRAM_I2C_DATA_BYTE, I2C_SLAVE_TYPE);//wm831x enter sleep mode
sram_i2c_delay(50);
sram_i2c_deinit(); //deinit i2c device
}
void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
{
uint8 slaveaddr;
uint16 slavereg;
unsigned int ret, mask, addr;
uint8 data[2];
sram_i2c_init(); //init i2c device
slaveaddr = I2C_SADDR; //slave device addr
slavereg = 0x4003; // reg addr
data[0] = 0x00; //clear i2c when read
data[1] = 0x00;
ret = sram_i2c_read(slaveaddr, slavereg, data, SRAM_I2C_DATA_BYTE, I2C_SLAVE_TYPE);
// print_Hex(data[0]); //read data saved in data
// print_Hex(data[1]); //read data saved in data
// sram_printch('\n');
data[0] &= ~(0x1<<6); //write data
sram_i2c_write(slaveaddr, slavereg, data, SRAM_I2C_DATA_BYTE, I2C_SLAVE_TYPE);//wm831x exit sleep mode
sram_i2c_delay(50);
sram_i2c_deinit(); //deinit i2c device
}
#endif
#endif

265
arch/arm/mach-rk29/spi_sram.c
View File

@@ -7,7 +7,21 @@
#include <asm/io.h>
#include <mach/gpio.h>
#include <asm/vfp.h>
#if 1
void __sramfunc sram_printch(char byte);
void __sramfunc printhex(unsigned int hex);
#define sram_printHX(a)
#else
#define sram_printch(a)
#define sram_printHX(a)
#endif
#define grf_readl(offset) readl(RK29_GRF_BASE + offset)
#define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
#define sram_udelay(usecs,a) LOOP((usecs)*LOOPS_PER_USEC)
#if defined(CONFIG_RK29_SPI_INSRAM)
@@ -17,7 +31,7 @@
#define SPI_SR_SPEED (2*SPI_MHZ)
#if defined(CONFIG_MACH_RK29_A22)||defined(CONFIG_MACH_RK29_PHONESDK)
#if defined(CONFIG_MACH_RK29_A22)||defined(CONFIG_MACH_RK29_PHONESDK)||defined(CONFIG_MACH_RK29_TD8801_V2)
#define SRAM_SPI_CH 1
#define SRAM_SPI_CS 1
@@ -85,15 +99,6 @@ SPI_BAUDR,
SPI_SER,
DATE_END,
};
#if 1
void __sramfunc sram_printch(char byte);
void __sramfunc printhex(unsigned int hex);
#define sram_printHX(a)
#else
#define sram_printch(a)
#define sram_printHX(a)
#endif
static u32 __sramdata spi_data[DATE_END]={};
#define sram_spi_dis() spi_writel(spi_readl(SPIM_ENR)&~(0x1<<0),SPIM_ENR)
@@ -105,10 +110,6 @@ void __sramfunc printhex(unsigned int hex);
#define spi_readl(offset) readl(SRAM_SPI_ADDRBASE + offset)
#define spi_writel(v, offset) writel(v, SRAM_SPI_ADDRBASE+ offset)
#define grf_readl(offset) readl(RK29_GRF_BASE + offset)
#define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
#define sram_udelay(usecs,a) LOOP((usecs)*LOOPS_PER_USEC)
#define SPI_GATE1_MASK 0xCF
@@ -362,6 +363,10 @@ void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
#endif
/*******************************************gpio*********************************************/
#ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
#define PM_GETGPIO_BASE(N) RK29_GPIO##N##_BASE
#define PM_GPIO_DR 0
#define PM_GPIO_DDR 0x4
#define PM_GPIO_INTEN 0x30
__sramdata u32 pm_gpio_base[7]=
{
RK29_GPIO0_BASE,
@@ -410,10 +415,240 @@ void __sramfunc pm_gpio_set(unsigned gpio,eGPIOPinDirection_t direction,eGPIOPin
}
}
#endif
/*****************************************gpio ctr*********************************************/
#if defined(CONFIG_RK29_GPIO_SUSPEND)
#define GRF_GPIO0_DIR 0x000
#define GRF_GPIO1_DIR 0x004
#define GRF_GPIO2_DIR 0x008
#define GRF_GPIO3_DIR 0x00c
#define GRF_GPIO4_DIR 0x010
#define GRF_GPIO5_DIR 0x014
#define GRF_GPIO0_DO 0x018
#define GRF_GPIO1_DO 0x01c
#define GRF_GPIO2_DO 0x020
#define GRF_GPIO3_DO 0x024
#define GRF_GPIO4_DO 0x028
#define GRF_GPIO5_DO 0x02c
#define GRF_GPIO0_EN 0x030
#define GRF_GPIO1_EN 0x034
#define GRF_GPIO2_EN 0x038
#define GRF_GPIO3_EN 0x03c
#define GRF_GPIO4_EN 0x040
#define GRF_GPIO5_EN 0x044
#define GRF_GPIO0L_IOMUX 0x048
#define GRF_GPIO0H_IOMUX 0x04c
#define GRF_GPIO1L_IOMUX 0x050
#define GRF_GPIO1H_IOMUX 0x054
#define GRF_GPIO2L_IOMUX 0x058
#define GRF_GPIO2H_IOMUX 0x05c
#define GRF_GPIO3L_IOMUX 0x060
#define GRF_GPIO3H_IOMUX 0x064
#define GRF_GPIO4L_IOMUX 0x068
#define GRF_GPIO4H_IOMUX 0x06c
#define GRF_GPIO5L_IOMUX 0x070
#define GRF_GPIO5H_IOMUX 0x074
typedef struct GPIO_IOMUX
{
unsigned int GPIOL_IOMUX;
unsigned int GPIOH_IOMUX;
}GPIO_IOMUX_PM;
//GRF Registers
typedef struct REG_FILE_GRF
{
unsigned int GRF_GPIO_DIR[6];
unsigned int GRF_GPIO_DO[6];
unsigned int GRF_GPIO_EN[6];
GPIO_IOMUX_PM GRF_GPIO_IOMUX[6];
unsigned int GRF_GPIO_PULL[7];
} GRF_REG_SAVE;
static GRF_REG_SAVE pm_grf;
int __sramdata crumode;
u32 __sramdata gpio2_pull,gpio6_pull;
//static GRF_REG_SAVE __sramdata pm_grf;
static void pm_keygpio_prepare(void)
{
gpio6_pull = grf_readl(GRF_GPIO6_PULL);
gpio2_pull = grf_readl(GRF_GPIO2_PULL);
}
void pm_keygpio_sdk_suspend(void)
{
pm_keygpio_prepare();
grf_writel(gpio6_pull|0x7f,GRF_GPIO6_PULL);//key pullup/pulldown disable
grf_writel(gpio2_pull|0x00000f30,GRF_GPIO2_PULL);
}
void pm_keygpio_sdk_resume(void)
{
grf_writel(gpio6_pull,GRF_GPIO6_PULL);//key pullup/pulldown enable
grf_writel(gpio2_pull,GRF_GPIO2_PULL);
}
void pm_keygpio_a22_suspend(void)
{
pm_keygpio_prepare();
grf_writel(gpio6_pull|0x7f,GRF_GPIO6_PULL);//key pullup/pulldown disable
grf_writel(gpio2_pull|0x00000900,GRF_GPIO2_PULL);
}
void pm_keygpio_a22_resume(void)
{
grf_writel(gpio6_pull,GRF_GPIO6_PULL);//key pullup/pulldown enable
grf_writel(gpio2_pull,GRF_GPIO2_PULL);
}
static void pm_spi_gpio_prepare(void)
{
pm_grf.GRF_GPIO_IOMUX[1].GPIOL_IOMUX = grf_readl(GRF_GPIO1L_IOMUX);
pm_grf.GRF_GPIO_IOMUX[2].GPIOH_IOMUX = grf_readl(GRF_GPIO2H_IOMUX);
pm_grf.GRF_GPIO_PULL[1] = grf_readl(GRF_GPIO1_PULL);
pm_grf.GRF_GPIO_PULL[2] = grf_readl(GRF_GPIO2_PULL);
pm_grf.GRF_GPIO_EN[1] = grf_readl(GRF_GPIO1_EN);
pm_grf.GRF_GPIO_EN[2] = grf_readl(GRF_GPIO2_EN);
}
void pm_spi_gpio_suspend(void)
{
int io1L_iomux;
int io2H_iomux;
int io1_pull,io2_pull;
int io1_en,io2_en;
pm_spi_gpio_prepare();
io1L_iomux = grf_readl(GRF_GPIO1L_IOMUX);
io2H_iomux = grf_readl(GRF_GPIO2H_IOMUX);
grf_writel(io1L_iomux&(~((0x03<<6)|(0x03 <<8))), GRF_GPIO1L_IOMUX);
grf_writel(io2H_iomux&0xffff0000, GRF_GPIO2H_IOMUX);
io1_pull = grf_readl(GRF_GPIO1_PULL);
io2_pull = grf_readl(GRF_GPIO2_PULL);
grf_writel(io1_pull|0x18,GRF_GPIO1_PULL);
grf_writel(io2_pull|0x00ff0000,GRF_GPIO2_PULL);
io1_en = grf_readl(GRF_GPIO1_EN);
io2_en = grf_readl(GRF_GPIO2_EN);
grf_writel(io1_en|0x18,GRF_GPIO1_EN);
grf_writel(io2_en|0x00ff0000,GRF_GPIO2_EN);
}
void pm_spi_gpio_resume(void)
{
grf_writel(pm_grf.GRF_GPIO_EN[1],GRF_GPIO1_EN);
grf_writel(pm_grf.GRF_GPIO_EN[2],GRF_GPIO2_EN);
grf_writel(pm_grf.GRF_GPIO_PULL[1],GRF_GPIO1_PULL);
grf_writel(pm_grf.GRF_GPIO_PULL[2],GRF_GPIO2_PULL);
grf_writel(pm_grf.GRF_GPIO_IOMUX[1].GPIOL_IOMUX, GRF_GPIO1L_IOMUX);
grf_writel(pm_grf.GRF_GPIO_IOMUX[2].GPIOH_IOMUX, GRF_GPIO2H_IOMUX);
}
void pm_gpio_suspend(void)
{
pm_spi_gpio_suspend(); // spi pullup/pulldown disable....
#if defined(CONFIG_MACH_RK29_PHONESDK)
{ pm_keygpio_sdk_suspend();// key pullup/pulldown disable.....
}
#endif
#if defined(CONFIG_MACH_RK29_A22)
{ pm_keygpio_a22_suspend();// key pullup/pulldown disable.....
}
#endif
}
void pm_gpio_resume(void)
{
pm_spi_gpio_resume(); // spi pullup/pulldown enable.....
#if defined(CONFIG_MACH_RK29_PHONESDK)
{ pm_keygpio_sdk_resume();// key pullup/pulldown enable.....
}
#endif
#if defined(CONFIG_MACH_RK29_A22)
{ pm_keygpio_a22_resume();// key pullup/pulldown enable.....
}
#endif
}
#else
void pm_gpio_suspend(void)
{}
void pm_gpio_resume(void)
{}
#endif
/*************************************neon powerdomain******************************/
#define vfpreg(_vfp_) #_vfp_
#define fmrx(_vfp_) ({ \
u32 __v; \
asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
: "=r" (__v) : : "cc"); \
__v; \
})
#define fmxr(_vfp_,_var_) \
asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
: : "r" (_var_) : "cc")
#define pmu_read(offset) readl(RK29_PMU_BASE + (offset))
#define pmu_write(offset, value) writel((value), RK29_PMU_BASE + (offset))
#define PMU_PG_CON 0x10
extern void vfp_save_state(void *location, u32 fpexc);
extern void vfp_load_state(void *location, u32 fpexc);
static u64 __sramdata saveptr[33]={};
void neon_powerdomain_off(void)
{
int ret,i=0;
int *p;
p=&saveptr;
unsigned int fpexc = fmrx(FPEXC); //get neon Logic gate
fmxr(FPEXC, fpexc | FPEXC_EN); //open neon Logic gate
for(i=0;i<34;i++){
vfp_save_state(p,fpexc); //save neon reg,32 D reg,2 control reg
p++;
}
fmxr(FPEXC, fpexc & ~FPEXC_EN); //close neon Logic gate
ret=pmu_read(PMU_PG_CON); //get power domain state
pmu_write(PMU_PG_CON,ret|(0x1<<1)); //powerdomain off neon
}
void neon_powerdomain_on(void)
{
int ret,i=0;
int *p;
p=&saveptr;
ret=pmu_read(PMU_PG_CON); //get power domain state
pmu_write(PMU_PG_CON,ret&~(0x1<<1)); //powerdomain on neon
sram_udelay(5000,24);
unsigned int fpexc = fmrx(FPEXC); //get neon Logic gate
fmxr(FPEXC, fpexc | FPEXC_EN); //open neon Logic gate
for(i=0;i<34;i++){
vfp_load_state(p,fpexc); //recovery neon reg, 32 D reg,2 control reg
p++;
}
fmxr(FPEXC, fpexc | FPEXC_EN); //open neon Logic gate
}
/*************************************************32k**************************************/
#ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
static int __sramdata crumode;
//static int __sramdata crumode;
void __sramfunc pm_clk_switch_32k(void)
{
int vol;

2
drivers/cmmb/cmmb_memory.c
View File

@@ -4,6 +4,8 @@
#include <linux/workqueue.h>
#include <asm/atomic.h>
#include <linux/vmalloc.h>
#include <linux/slab.h>
#if 1
#define DBGERR(x...) printk(KERN_INFO x)
#else

1
drivers/cmmb/siano/smscoreapi.c
View File

@@ -37,6 +37,7 @@
#include "smsendian.h"
#include "sms-cards.h"
#include <mach/gpio.h>
#include <linux/slab.h>
#define MAX_GPIO_PIN_NUMBER 31

3
drivers/cmmb/siano/smsspiphy.h
View File

@@ -42,5 +42,8 @@ int smsspibus_ssp_resume(void* context);
unsigned int cmmb_pw_rst;
unsigned int cmmb_irq;
void (*io_init_mux)(void);
void (*cmmb_io_pm)(void);
void (*cmmb_power_on)(void);
void (*cmmb_power_down)(void);
};
#endif /* __SMS_SPI_PHY_H__ */

2
drivers/video/backlight/rk29_buttonlight.c
View File

@@ -76,7 +76,7 @@ static int rk29_button_light_probe(struct platform_device *pdev)
{
struct rk29_button_light_info *button_light_info = pdev->dev.platform_data;
rk29_button_light_device = backlight_device_register("rk28_button_light", &pdev->dev, NULL, &rk29_button_light_ops);
rk29_button_light_device = backlight_device_register("rk28_button_light", &pdev->dev, NULL, &rk29_button_light_ops,NULL);
if (!rk29_button_light_device) {
DBG("rk29_button_light_probe error\n");
return -ENODEV;

4
drivers/video/rk29_fb.c
View File

@@ -3671,7 +3671,11 @@ static void __exit rk29fb_exit(void)
platform_driver_unregister(&rk29fb_driver);
}
#if defined(CONFIG_MACH_RK29_TD8801_V2)
rootfs_initcall(rk29fb_init);
#else
fs_initcall(rk29fb_init);
#endif
module_exit(rk29fb_exit);

52
include/linux/smp_lock.h Normal file
View File

@@ -0,0 +1,52 @@
#ifndef __LINUX_SMPLOCK_H
#define __LINUX_SMPLOCK_H
#ifdef CONFIG_LOCK_KERNEL
#include <linux/sched.h>
#define kernel_locked() (current->lock_depth >= 0)
extern int __lockfunc __reacquire_kernel_lock(void);
extern void __lockfunc __release_kernel_lock(void);
/*
* Release/re-acquire global kernel lock for the scheduler
*/
#define release_kernel_lock(tsk) do { \
if (unlikely((tsk)->lock_depth >= 0)) \
__release_kernel_lock(); \
} while (0)
static inline int reacquire_kernel_lock(struct task_struct *task)
{
if (unlikely(task->lock_depth >= 0))
return __reacquire_kernel_lock();
return 0;
}
extern void __lockfunc lock_kernel(void) __acquires(kernel_lock);
extern void __lockfunc unlock_kernel(void) __releases(kernel_lock);
/*
* Various legacy drivers don't really need the BKL in a specific
* function, but they *do* need to know that the BKL became available.
* This function just avoids wrapping a bunch of lock/unlock pairs
* around code which doesn't really need it.
*/
static inline void cycle_kernel_lock(void)
{
lock_kernel();
unlock_kernel();
}
#else
#define lock_kernel() do { } while(0)
#define unlock_kernel() do { } while(0)
#define release_kernel_lock(task) do { } while(0)
#define cycle_kernel_lock() do { } while(0)
#define reacquire_kernel_lock(task) 0
#define kernel_locked() 1
#endif /* CONFIG_LOCK_KERNEL */
#endif /* __LINUX_SMPLOCK_H */

1
include/media/v4l2-subdev.h
View File

@@ -511,6 +511,7 @@ struct v4l2_subdev {
/* pointer to private data */
void *dev_priv;
void *host_priv;
void *priv;
/* subdev device node */
struct video_device devnode;
/* number of events to be allocated on open */