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hdmirx: optimize print and coding style [1/1]

Browse Source 
PD#SWPL-6400

Problem:
need sync code with mainline

Solution:
sync mainline's print and coding style

Verify:
verify by marconi

Change-Id: I1934cf01f8e1ff87a0c9ab59a7288d2b6edaff84
Signed-off-by: Lei Qian <lei.qian@amlogic.com>
This commit is contained in:
Lei Qian
2019-05-05 16:40:12 +08:00
committed by Luke Go
parent d4da3b84ac
commit 4739b42a9f
1 changed files with 7 additions and 9 deletions
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16
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
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@@ -3804,7 +3804,6 @@ void aml_phy_pll_setting(void)
(M <= 80)) {
data2 = 0x300b8f30 | od2;
m_div = 2;
rx_pr("1-m=%d\n", m_div);
} else {
data2 = 0x300d8f30 | od2;
m_div = 1;
@@ -3821,25 +3820,24 @@ void aml_phy_pll_setting(void)
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2);
udelay(1);
/*cntl0 M <7:0> N<14:10>*/
data = 0x00090000 & 0xffff8300;
data = 0x00090000;
data |= M * m_div;
data |= (N << 10);
rx_pr("2-m=%d\n", m_div);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x20000000);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x30000000);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x20000000);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x30000000);
udelay(5);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2|0x00800000);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2 | 0x00800000);
udelay(5);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x34000000);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x34000000);
udelay(5);
if (m_div == 2) {
m_div = 1;
data &= 0xffffff00;
data |= M * m_div;
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x34000000);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x34000000);
}
data &= 0xdfffffff;
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x14000000);
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data | 0x14000000);
/* bit'5: force lock bit'2: improve phy ldo voltage */
wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x0000303c);