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UPSTREAM: arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.ASIDBits

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For some reason we refer to ID_AA64MMFR0_EL1.ASIDBits as ASID. Add BITS
into the name, bringing the naming into sync with DDI0487H.a. Due to the
large amount of MixedCase in this register which isn't really consistent
with either the kernel style or the majority of the architecture the use of
upper case is preserved. No functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-10-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 07d7d848b9)
Signed-off-by: Will Deacon <willdeacon@google.com>
Bug: 233587962
Bug: 233588291
Change-Id: Ibd4a7ba7459058d07be7b749b66ea28edb439121
This commit is contained in:
Mark Brown
2022-09-05 23:54:06 +01:00
committed by Will Deacon
parent 665c8a7a28
commit 475c494b5d
5 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/include/asm/sysreg.h
View File

@@ -933,11 +933,11 @@
#define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
#define ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
#define ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
#define ID_AA64MMFR0_EL1_ASID_SHIFT 4
#define ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
#define ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
#define ID_AA64MMFR0_EL1_ASID_8 0x0
#define ID_AA64MMFR0_EL1_ASID_16 0x2
#define ID_AA64MMFR0_EL1_ASIDBITS_8 0x0
#define ID_AA64MMFR0_EL1_ASIDBITS_16 0x2
#define ID_AA64MMFR0_EL1_TGRAN4_NI 0xf
#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0

2
arch/arm64/kernel/cpufeature.c
View File

@@ -351,7 +351,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
/* Linux shouldn't care about secure memory */
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASID_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0),
/*
* Differing PARange is fine as long as all peripherals and memory are mapped
* within the minimum PARange of all CPUs

2
arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
View File

@@ -87,7 +87,7 @@
*/
#define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\
FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \
FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASID), ID_AA64MMFR0_EL1_ASID_16) \
FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \
)
/*

6
arch/arm64/mm/context.c
View File

@@ -43,17 +43,17 @@ static u32 get_cpu_asid_bits(void)
{
u32 asid;
int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1),
ID_AA64MMFR0_EL1_ASID_SHIFT);
ID_AA64MMFR0_EL1_ASIDBITS_SHIFT);
switch (fld) {
default:
pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",
smp_processor_id(), fld);
fallthrough;
case ID_AA64MMFR0_EL1_ASID_8:
case ID_AA64MMFR0_EL1_ASIDBITS_8:
asid = 8;
break;
case ID_AA64MMFR0_EL1_ASID_16:
case ID_AA64MMFR0_EL1_ASIDBITS_16:
asid = 16;
}

2
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
View File

@@ -434,7 +434,7 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smmu)
return false;
/* We can support bigger ASIDs than the CPU, but not smaller */
fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_ASID_SHIFT);
fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT);
asid_bits = fld ? 16 : 8;
if (smmu->asid_bits < asid_bits)
return false;