clock: 融合2.6.25 release v1.06

* clock设置pll频率采用渐进方式。
* 变频使用192M和576M，保证apb频率固定为48M。

arch/arm/mach-rk2818/cpufreq.c

@@ -18,7 +18,11 @@
 #include <linux/err.h>
 #include <linux/init.h>
 
-static struct cpufreq_frequency_table *freq_table;
+static struct cpufreq_frequency_table freq_table[] = {
+	{ .frequency = 192000 },
+	{ .frequency = 576000 },
+	{ .frequency = CPUFREQ_TABLE_END },
+};
 static struct clk *arm_clk;
 
 static int rk2818_cpufreq_verify(struct cpufreq_policy *policy)
@@ -65,10 +69,6 @@ static int __init rk2818_cpufreq_init(struct cpufreq_policy *policy)
 	if (policy->cpu != 0)
 		return -EINVAL;
 
-	clk_init_cpufreq_table(&freq_table);
-	if (!freq_table)
-		return -EINVAL;
-
 	BUG_ON(cpufreq_frequency_table_cpuinfo(policy, freq_table));
 	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
 	policy->cur = clk_get_rate(arm_clk) / 1000;

arch/arm/mach-rk2818/include/mach/scu.h

@@ -86,6 +86,7 @@ enum scu_clk_gate
 	CLK_GATE_MAX,
 };
 
+/* Register definitions */
 #define SCU_APLL_CON		0x00
 #define SCU_DPLL_CON		0x04
 #define SCU_CPLL_CON		0x08
@@ -101,4 +102,27 @@ enum scu_clk_gate
 #define SCU_CPUPD		0x30
 #define SCU_CLKSEL2_CON		0x34
 
+#include <asm/tcm.h>
+
+#define DDR_SAVE_SP		do { save_sp = ddr_save_sp((DTCM_END&(~7))); } while (0)
+#define DDR_RESTORE_SP		do { ddr_save_sp(save_sp); } while (0)
+unsigned long ddr_save_sp( unsigned long new_sp );
+extern unsigned long save_sp;
+extern int __tcmdata ddr_disabled;
+
+/*
+ * delay at itcm. one loops == 6 arm instruction 
+ * at 600M,about 6,000,0 for 1ms delay.
+ */
+extern void __tcmfunc ddr_pll_delay( int loops ) ;
+
+/**
+ * tcm_udelay - delay usecs microseconds in tcm
+ * @usecs: in microseconds
+ * @arm_freq_mhz: arm frequency in MHz
+ *
+ * for example when arm run at slow mode, call tcm_udelay(usecs, 24)
+ */
+extern void __tcmfunc tcm_udelay(unsigned long usecs, unsigned long arm_freq_mhz);
+
 #endif