media: i2c: rk628: add csc matrix support

Change-Id: If48350f4e9555852785bb2188ab29ae3c0b99961
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>

drivers/media/i2c/rk628/Makefile

@@ -2,7 +2,7 @@
 #
 # Makefile for the Rockchip RK628 display bridge driver.
 #
-video-rk628-objs	:= rk628.o rk628_cru.o rk628_hdmirx.o rk628_dsi.o rk628_combrxphy.o rk628_combtxphy.o
+video-rk628-objs	:= rk628.o rk628_cru.o rk628_hdmirx.o rk628_dsi.o rk628_combrxphy.o rk628_combtxphy.o rk628_post_process.o
 obj-$(CONFIG_VIDEO_RK628)	+= video-rk628.o
 
 rk628-csi-objs	:= rk628_csi_v4l2.o

drivers/media/i2c/rk628/rk628.h

@@ -91,6 +91,8 @@
 #define SW_SPLIT_MODE(x)		UPDATE(x, 1, 1)
 #define SW_SPLIT_EN			BIT(0)
 #define GRF_CSC_CTRL_CON		0x0038
+#define SW_Y2R_MODE(x)			HIWORD_UPDATE(x, 13, 12)
+#define SW_FROM_CSC_MATRIX_EN(x)	HIWORD_UPDATE(x, 11, 11)
 #define SW_YUV2VYU_SWP(x)		HIWORD_UPDATE(x, 8, 8)
 #define SW_R2Y_EN(x)			HIWORD_UPDATE(x, 4, 4)
 #define SW_Y2R_EN(x)			HIWORD_UPDATE(x, 0, 0)
@@ -207,6 +209,14 @@
 #define GRF_OS_REG1			0x0144
 #define GRF_OS_REG2			0x0148
 #define GRF_OS_REG3			0x014c
+#define GRF_CSC_MATRIX_COE01_COE00	0x01a0
+#define GRF_CSC_MATRIX_COE10_COE02	0x01a4
+#define GRF_CSC_MATRIX_COE12_COE11	0x01a8
+#define GRF_CSC_MATRIX_COE21_COE20	0x01ac
+#define GRF_CSC_MATRIX_COE22		0x01b0
+#define GRF_CSC_MATRIX_OFFSET0		0x01b4
+#define GRF_CSC_MATRIX_OFFSET1		0x01b8
+#define GRF_CSC_MATRIX_OFFSET2		0x01bc
 #define GRF_SOC_VERSION			0x0200
 #define GRF_MAX_REGISTER		GRF_SOC_VERSION
 

drivers/media/i2c/rk628/rk628_csi_v4l2.c

@@ -43,6 +43,7 @@
 #include "rk628_dsi.h"
 #include "rk628_hdmirx.h"
 #include "rk628_mipi_dphy.h"
+#include "rk628_post_process.h"
 
 static int debug;
 module_param(debug, int, 0644);
@@ -1070,18 +1071,22 @@ static void rk628_csi_set_csi(struct v4l2_subdev *sd)
 	video_fmt = (val & VIDEO_FORMAT_MASK) >> 5;
 	v4l2_dbg(1, debug, &csi->sd, "%s PDEC_AVI_PB:%#x, video format:%d\n",
 			__func__, val, video_fmt);
-	if (video_fmt) {
-		/* yuv data: cfg SW_YUV2VYU_SWP */
-		rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
+	if (csi->rk628->version == RK628D_VERSION) {
+		if (video_fmt) {
+			/* yuv data: cfg SW_YUV2VYU_SWP */
+			rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
 				SW_YUV2VYU_SWP(1) |
 				SW_R2Y_EN(0));
-	} else {
-		/* rgb data: cfg SW_R2Y_EN */
-		rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
+		} else {
+			/* rgb data: cfg SW_R2Y_EN */
+			rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
 				SW_YUV2VYU_SWP(0) |
 				SW_R2Y_EN(1) | SW_R2Y_CSC_MODE(2));
+		}
+	} else {
+		rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON, SW_YUV2VYU_SWP(1));
+		rk628_post_process_csc_en(csi->rk628);
 	}
-
 	/* if avi packet is not stable, reset ctrl*/
 	if (!avi_rdy) {
 		csi->nosignal = true;

drivers/media/i2c/rk628/rk628_hdmirx.c

@@ -1008,3 +1008,19 @@ int rk628_hdmirx_get_timings(struct rk628 *rk628,
 	return ret;
 }
 EXPORT_SYMBOL(rk628_hdmirx_get_timings);
+
+u8 rk628_hdmirx_get_range(struct rk628 *rk628)
+{
+	u32 val;
+	u8 color_range;
+
+	rk628_i2c_read(rk628, HDMI_RX_PDEC_AVI_PB, &val);
+	color_range = (val & RGB_COLORRANGE_MASK) >> 18;
+	if (color_range == 0x1)
+		color_range = CSC_LIMIT_RANGE;
+	else
+		color_range = CSC_FULL_RANGE;
+
+	return color_range;
+}
+EXPORT_SYMBOL(rk628_hdmirx_get_range);

drivers/media/i2c/rk628/rk628_hdmirx.h

@@ -250,6 +250,8 @@
 #define HDMI_RX_PDEC_AVI_PB		(HDMI_RX_BASE + 0x03a4)
 #define VIDEO_FORMAT_MASK		GENMASK(6, 5)
 #define VIDEO_FORMAT(x)			UPDATE(x, 6, 5)
+#define RGB_COLORRANGE_MASK		GENMASK(19, 18)
+#define RGB_COLORRANGE(x)		UPDATE(x, 19, 18)
 #define ACT_INFO_PRESENT_MASK		BIT(4)
 #define HDMI_RX_PDEC_ACR_CTS		(HDMI_RX_BASE + 0x0390)
 #define HDMI_RX_PDEC_ACR_N		(HDMI_RX_BASE + 0x0394)
@@ -378,6 +380,11 @@
 #define HDMIRX_MODETCLK_CNT_NUM		1000
 #define HDMIRX_MODETCLK_HZ		49500000
 
+enum color_range {
+	CSC_LIMIT_RANGE,
+	CSC_FULL_RANGE,
+};
+
 enum bus_format {
 	BUS_FMT_RGB = 0,
 	BUS_FMT_YUV422 = 1,
@@ -427,5 +434,6 @@ void rk628_set_bg_enable(struct rk628 *rk628, bool en);
 u32 rk628_hdmirx_get_tmdsclk_cnt(struct rk628 *rk628);
 int rk628_hdmirx_get_timings(struct rk628 *rk628,
 			     struct v4l2_dv_timings *timings);
+u8 rk628_hdmirx_get_range(struct rk628 *rk628);
 
 #endif

drivers/media/i2c/rk628/rk628_post_process.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co. Ltd.
+ *
+ */
+
+#ifndef POST_PROCESS_H
+#define POST_PROCESS_H
+
+void rk628_post_process_csc_en(struct rk628 *rk628);
+void rk628_post_process_csc_dis(struct rk628 *rk628);
+
+#endif