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drm/rockchip: vop: Add dclk rate count for RK3576

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RK3576 supports calculating the exact dclk from the known hclk rate.

Change-Id: I06f3f59118bc6627b9bb92d0e9aedf1848e5c72c
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
This commit is contained in:
Chaoyi Chen
2025-01-23 07:57:14 +00:00
parent ff7af21e33
commit 48980901a1
4 changed files with 45 additions and 0 deletions
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4
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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@@ -1078,6 +1078,10 @@ struct vop2_video_port_regs {
struct vop_reg crc_val;
struct vop_reg crc_check_en;
struct vop_reg crc_check_val;
/* clk calc*/
struct vop_reg calc_clk_en;
struct vop_reg calc_dclk_cnt;
};
struct vop2_power_domain_regs {

29
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -8305,6 +8305,7 @@ static int vop2_crtc_debugfs_init(struct drm_minor *minor, struct drm_crtc *crtc
rockchip_drm_add_dump_buffer(crtc, vop2->debugfs);
rockchip_drm_debugfs_add_color_bar(crtc, vop2->debugfs);
rockchip_drm_debugfs_add_regs_write(crtc, vop2->debugfs);
rockchip_drm_debugfs_add_dclk_rate(crtc, vop2->debugfs);
#endif
for (i = 0; i < ARRAY_SIZE(vop2_debugfs_files); i++)
vop2->debugfs_files[i].data = vop2;
@@ -8627,6 +8628,31 @@ static void vop2_iommu_fault_handler(struct drm_crtc *crtc, struct iommu_domain
rockchip_drm_send_error_event(private, ROCKCHIP_DRM_ERROR_EVENT_IOMMU_FAULT);
}
#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
static unsigned long vop2_crtc_get_dclk_rate(struct drm_crtc *crtc)
{
struct vop2_video_port *vp = to_vop2_video_port(crtc);
struct vop2 *vop2 = vp->vop2;
unsigned long rate, count;
/* not support */
if (!vp->regs->calc_dclk_cnt.mask)
return 0;
VOP_MODULE_SET(vop2, vp, calc_clk_en, 1);
usleep_range(500, 1000);
count = VOP_MODULE_GET(vop2, vp, calc_dclk_cnt);
rate = clk_get_rate(vop2->hclk);
/* calc_dclk_cnt is the count number when hclk counts to 5000 */
rate = rate / 5000 * count;
VOP_MODULE_SET(vop2, vp, calc_clk_en, 0);
return rate;
}
#endif
static const struct rockchip_crtc_funcs private_crtc_funcs = {
.loader_protect = vop2_crtc_loader_protect,
.cancel_pending_vblank = vop2_crtc_cancel_pending_vblank,
@@ -8649,6 +8675,9 @@ static const struct rockchip_crtc_funcs private_crtc_funcs = {
.set_aclk = vop2_set_aclk_rate,
.get_crc = vop2_crtc_get_crc,
.iommu_fault_handler = vop2_iommu_fault_handler,
#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
.crtc_get_dclk_rate = vop2_crtc_get_dclk_rate,
#endif
};
static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,

9
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
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@@ -1672,6 +1672,9 @@ static const struct vop2_video_port_regs rk3576_vop_vp0_regs = {
.post_urgency_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 8),
.post_urgency_thl = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0xf, 16),
.post_urgency_thh = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0xf, 20),
.calc_dclk_cnt = VOP_REG(RK3576_VP0_POST_CLK_CNT, 0x7fff, 0),
.calc_clk_en = VOP_REG(RK3576_VP0_POST_CLK_CNT, 0x1, 15),
};
static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
@@ -1760,6 +1763,9 @@ static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
.post_urgency_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 8),
.post_urgency_thl = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0xf, 16),
.post_urgency_thh = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0xf, 20),
.calc_dclk_cnt = VOP_REG(RK3576_VP1_POST_CLK_CNT, 0x7fff, 0),
.calc_clk_en = VOP_REG(RK3576_VP1_POST_CLK_CNT, 0x1, 15),
};
static const struct vop2_video_port_regs rk3576_vop_vp2_regs = {
@@ -1845,6 +1851,9 @@ static const struct vop2_video_port_regs rk3576_vop_vp2_regs = {
.post_urgency_en = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 8),
.post_urgency_thl = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0xf, 16),
.post_urgency_thh = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0xf, 20),
.calc_dclk_cnt = VOP_REG(RK3576_VP2_POST_CLK_CNT, 0x7fff, 0),
.calc_clk_en = VOP_REG(RK3576_VP2_POST_CLK_CNT, 0x1, 15),
};
static const struct vop3_ovl_regs rk3576_vop_vp0_ovl_regs = {

3
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
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@@ -1163,6 +1163,7 @@
#define RK3576_VP0_POST_DITHER_FRC_0 0xCA0
#define RK3576_VP0_POST_DITHER_FRC_1 0xCA4
#define RK3576_VP0_POST_DITHER_FRC_2 0xCA8
#define RK3576_VP0_POST_CLK_CNT 0xCF4
#define RK3562_VP0_MCU_CTRL 0xCF8
#define RK3562_VP0_MCU_RW_BYPASS_PORT 0xCFC
@@ -1207,6 +1208,7 @@
#define RK3576_VP1_POST_DITHER_FRC_0 0xDA0
#define RK3576_VP1_POST_DITHER_FRC_1 0xDA4
#define RK3576_VP1_POST_DITHER_FRC_2 0xDA8
#define RK3576_VP1_POST_CLK_CNT 0xDF4
#define RK3562_VP1_MCU_CTRL 0xDF8
#define RK3562_VP1_MCU_RW_BYPASS_PORT 0xDFC
@@ -1237,6 +1239,7 @@
#define RK3568_VP2_BCSH_BCS 0xE64
#define RK3568_VP2_BCSH_H 0xE68
#define RK3568_VP2_BCSH_COLOR_BAR 0xE6C
#define RK3576_VP2_POST_CLK_CNT 0xEF4
#define RK3576_VP2_MCU_CTRL 0xEF8
#define RK3576_VP2_MCU_RW_BYPASS_PORT 0xEFC