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FROMLIST: usb: dwc2: assert phy reset when waking up in rk3288 platform

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On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).

We can get the PHY out of its bad state by asserting its "port reset",
but unfortunately that seems to assert a reset onto the USB bus so it
could confuse things if we don't actually deenumerate / reenumerate the
device.

We can also get the PHY out of its bad state by fully resetting it using
the reset from the CRU (clock reset unit) in chip, which does a more full
reset.  The CRU-based reset appears to actually cause devices on the bus
to be removed and reinserted, which fixes the problem (albeit in a hacky
way).

It's unfortunate that we need to do a full re-enumeration of devices at
wakeup time, but this is better than alternative of letting the bus get
wedged.

Change-Id: I3120a38a7f646a9d244f04bd2dcfef7474a4a6d1
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(am from https://mail-archive.com/linux-kernel@vger.kernel.org/msg1254059.html)
This commit is contained in:
Jacob Chen
2016-12-07 17:29:06 +08:00
committed by Tao Huang
parent e09c7baf75
commit 48ca5779e3
3 changed files with 23 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/usb/dwc2/core.h
View File

@@ -1021,6 +1021,7 @@ struct dwc2_hsotg {
u16 frame_number;
struct phy *phy;
struct work_struct phy_rst_work;
struct usb_phy *uphy;
struct dwc2_hsotg_plat *plat;
struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];

13
drivers/usb/dwc2/core_intr.c
View File

@@ -396,6 +396,7 @@ static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
{
int ret;
struct device_node *np = hsotg->dev->of_node;
/* Clear interrupt */
dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
@@ -435,6 +436,18 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
/* Restart the Phy Clock */
pcgcctl &= ~PCGCTL_STOPPCLK;
dwc2_writel(hsotg, pcgcctl, PCGCTL);
/*
* It is a quirk in Rockchip RK3288, causing by
* a hardware bug. This will propagate out and
* eventually we'll re-enumerate the device.
* Not great but the best we can do.
*/
if (of_device_is_compatible(np, "rockchip,rk3288-usb")) {
/* FIXME: wkp_timer might run early than phy_rst_work */
schedule_work(&hsotg->phy_rst_work);
}
mod_timer(&hsotg->wkp_timer,
jiffies + msecs_to_jiffies(71));
} else {

9
drivers/usb/dwc2/platform.c
View File

@@ -208,6 +208,14 @@ int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
return ret;
}
/* Only used to reset usb phy at interrupter runtime */
static void dwc2_reset_phy_work(struct work_struct *data)
{
struct dwc2_hsotg *hsotg = container_of(data, struct dwc2_hsotg,
phy_rst_work);
phy_reset(hsotg->phy);
}
static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
{
int i, ret;
@@ -252,6 +260,7 @@ static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
return ret;
}
}
INIT_WORK(&hsotg->phy_rst_work, dwc2_reset_phy_work);
if (!hsotg->phy) {
hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);