shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 20:07:46 +09:00
Code Issues Packages Projects Releases Wiki Activity

mtd: fix the macro of BCH mode index

Browse Source 
PD#155673: mtd: fix the macro of BCH mode index

Change-Id: Iee7d1b11569411c2edcd43e2355299735b7dd1d1
Signed-off-by: Yi Zeng <yi.zeng@amlogic.com>
This commit is contained in:
Yi Zeng
2017-11-28 19:55:50 +08:00
parent 2dc5888c59
commit 49832da244
2 changed files with 9 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/amlogic/mtd/aml_hwctrl.h
View File

@@ -439,21 +439,16 @@ static inline void amlnf_clr_reg32_mask(uint32_t *_reg,
*#define NFC_CMD_I_ADR(addr) NFC_CMD_ADI(addr), NFC_CMD_ADI(addr)
*/
#define NAND_ECC_NONE (0x0)
#define NAND_ECC_BCH8 (0x1)
#define NAND_ECC_BCH8_1K (0x2)
#define NAND_ECC_BCH16_1K (0x3)
#define NAND_ECC_BCH24_1K (0x4)
#define NAND_ECC_BCH24_1K_M8 (0x3)
#define NAND_ECC_BCH30_1K (0x5)
#define NAND_ECC_BCH30_1K_M8 (0x4)
#define NAND_ECC_BCH40_1K (0x6)
#define NAND_ECC_BCH40_1K_M8 (0x5)
#define NAND_ECC_BCH50_1K_M8 (0x6)
#define NAND_ECC_NONE (0x0)
#define NAND_ECC_BCH8 (0x1)
#define NAND_ECC_BCH8_1K (0x2)
#define NAND_ECC_BCH24_1K (0x3)
#define NAND_ECC_BCH30_1K (0x4)
#define NAND_ECC_BCH40_1K (0x5)
#define NAND_ECC_BCH50_1K (0x6)
/*NAND_ECC_BCH50_1K only for mtd for general*/
#define NAND_ECC_BCH50_1K (0x6)
#define NAND_ECC_BCH60_1K (0x7)
#define NAND_ECC_BCH_SHORT (0x8)
#define NAND_ECC_BCH60_1K (0x7)
#define NAND_ECC_BCH_SHORT (0x8)
#define PER_INFO_BYTE 8

11
drivers/amlogic/mtd/m3_nand.c
View File

@@ -436,17 +436,6 @@ static int m3_nand_options_confirm(struct aml_nand_chip *aml_chip)
aml_chip->ecc_max = 8;
chip->ecc.steps = mtd->writesize / chip->ecc.size;
break;
/*don't support for new chip(greater than m8)*/
case NAND_ECC_BCH16_1K_MODE:
chip->ecc.strength = 16;
chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
chip->ecc.bytes = NAND_BCH16_1K_ECC_SIZE;
aml_chip->bch_mode = NAND_ECC_BCH16_1K;
aml_chip->user_byte_mode = 2;
aml_chip->ecc_cnt_limit = 14;
aml_chip->ecc_max = 16;
chip->ecc.steps = mtd->writesize / chip->ecc.size;
break;
case NAND_ECC_BCH24_1K_MODE:
chip->ecc.strength = 24;