shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-10 04:48:04 +09:00
Code Issues Packages Projects Releases Wiki Activity

Merge commit '50f19f66e690c3f7b99611f961c4868154b46e9c'

Browse Source 
* commit '50f19f66e690c3f7b99611f961c4868154b46e9c':
  soc: rockchip: pm_config: better module support
  soc: rockchip: rockchip_system_monitor: modify ebc dmc policy
  PM / devfreq: rockchip_dmc: Add ebc system status support
  drm/rockchip: vop2: Set single vop status when only one active video port
  net: wireless: rockchip_wlan: bcmdhd: Reset PCIe when wifi reg on
  PCI: dw: rockchip: Support rockchip_dw_pcie_pm_ctrl_for_user
  arm64: dts: rockchip: add rk3562-iotest-lp3-v10.dtsi for iotest board
  media: i2c: fixes error of techpoint driver

Change-Id: I1ca8bd8d1ca4c08fd8dcc782826120ba0e96ff2b
This commit is contained in:
Tao Huang
2024-05-23 10:28:25 +08:00
parent c4e158f76d 50f19f66e6
commit 49bbbba51c
14 changed files with 695 additions and 720 deletions
Download Patch File Download Diff File Expand all files Collapse all files

94
arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10-linux.dts
View File

@@ -1,98 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3562.dtsi"
#include "rk3562-iotest-lp3-v10.dtsi"
#include "rk3562-linux.dtsi"
/ {
model = "Rockchip RK3562 IOTEST LP3 V10 Board";
compatible = "rockchip,rk3562-iotest-lp3-v10", "rockchip,rk3562";
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc3v3_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
dsm_sound: dsm-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,dsm-sound";
simple-audio-card,bitclock-master = <&sndcodec>;
simple-audio-card,frame-master = <&sndcodec>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&sai1>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&dsm>;
};
};
};
#include "rk3562-rk809.dtsi"
&combphy_pu {
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usbdrd30 {
status = "okay";
};
&usbdrd_dwc3 {
status = "okay";
dr_mode = "otg";
extcon = <&u2phy>;
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
};

572
arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dts
View File

@@ -1,576 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3562.dtsi"
#include "rk3562-iotest-lp3-v10.dtsi"
#include "rk3562-android.dtsi"
#include "rk3562-rk809.dtsi"
#include <dt-bindings/display/drm_mipi_dsi.h>
/ {
model = "Rockchip RK3562 IOTEST LP3 V10 Board";
compatible = "rockchip,rk3562-iotest-lp3-v10", "rockchip,rk3562";
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm5 0 25000 0>;
brightness-levels = <
0 20 20 21 21 22 22 23
23 24 24 25 25 26 26 27
27 28 28 29 29 30 30 31
31 32 32 33 33 34 34 35
35 36 36 37 37 38 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255
>;
default-brightness-level = <200>;
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
test-power {
status = "okay";
};
vcc3v3_lcd_n: vcc3v3-lcd0-n {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd_n";
gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc3v3_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
dsm_sound: dsm-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,dsm-sound";
simple-audio-card,bitclock-master = <&sndcodec>;
simple-audio-card,frame-master = <&sndcodec>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&sai1>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&dsm>;
};
};
};
&combphy_pu {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&display_subsystem {
status = "okay";
};
&dsi {
status = "okay";
//rockchip,lane-rate = <1000>;
dsi_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight>;
reset-delay-ms = <60>;
enable-delay-ms = <60>;
prepare-delay-ms = <60>;
unprepare-delay-ms = <60>;
disable-delay-ms = <60>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
23 00 02 FE 21
23 00 02 04 00
23 00 02 00 64
23 00 02 2A 00
23 00 02 26 64
23 00 02 54 00
23 00 02 50 64
23 00 02 7B 00
23 00 02 77 64
23 00 02 A2 00
23 00 02 9D 64
23 00 02 C9 00
23 00 02 C5 64
23 00 02 01 71
23 00 02 27 71
23 00 02 51 71
23 00 02 78 71
23 00 02 9E 71
23 00 02 C6 71
23 00 02 02 89
23 00 02 28 89
23 00 02 52 89
23 00 02 79 89
23 00 02 9F 89
23 00 02 C7 89
23 00 02 03 9E
23 00 02 29 9E
23 00 02 53 9E
23 00 02 7A 9E
23 00 02 A0 9E
23 00 02 C8 9E
23 00 02 09 00
23 00 02 05 B0
23 00 02 31 00
23 00 02 2B B0
23 00 02 5A 00
23 00 02 55 B0
23 00 02 80 00
23 00 02 7C B0
23 00 02 A7 00
23 00 02 A3 B0
23 00 02 CE 00
23 00 02 CA B0
23 00 02 06 C0
23 00 02 2D C0
23 00 02 56 C0
23 00 02 7D C0
23 00 02 A4 C0
23 00 02 CB C0
23 00 02 07 CF
23 00 02 2F CF
23 00 02 58 CF
23 00 02 7E CF
23 00 02 A5 CF
23 00 02 CC CF
23 00 02 08 DD
23 00 02 30 DD
23 00 02 59 DD
23 00 02 7F DD
23 00 02 A6 DD
23 00 02 CD DD
23 00 02 0E 15
23 00 02 0A E9
23 00 02 36 15
23 00 02 32 E9
23 00 02 5F 15
23 00 02 5B E9
23 00 02 85 15
23 00 02 81 E9
23 00 02 AD 15
23 00 02 A9 E9
23 00 02 D3 15
23 00 02 CF E9
23 00 02 0B 14
23 00 02 33 14
23 00 02 5C 14
23 00 02 82 14
23 00 02 AA 14
23 00 02 D0 14
23 00 02 0C 36
23 00 02 34 36
23 00 02 5D 36
23 00 02 83 36
23 00 02 AB 36
23 00 02 D1 36
23 00 02 0D 6B
23 00 02 35 6B
23 00 02 5E 6B
23 00 02 84 6B
23 00 02 AC 6B
23 00 02 D2 6B
23 00 02 13 5A
23 00 02 0F 94
23 00 02 3B 5A
23 00 02 37 94
23 00 02 64 5A
23 00 02 60 94
23 00 02 8A 5A
23 00 02 86 94
23 00 02 B2 5A
23 00 02 AE 94
23 00 02 D8 5A
23 00 02 D4 94
23 00 02 10 D1
23 00 02 38 D1
23 00 02 61 D1
23 00 02 87 D1
23 00 02 AF D1
23 00 02 D5 D1
23 00 02 11 04
23 00 02 39 04
23 00 02 62 04
23 00 02 88 04
23 00 02 B0 04
23 00 02 D6 04
23 00 02 12 05
23 00 02 3A 05
23 00 02 63 05
23 00 02 89 05
23 00 02 B1 05
23 00 02 D7 05
23 00 02 18 AA
23 00 02 14 36
23 00 02 42 AA
23 00 02 3D 36
23 00 02 69 AA
23 00 02 65 36
23 00 02 8F AA
23 00 02 8B 36
23 00 02 B7 AA
23 00 02 B3 36
23 00 02 DD AA
23 00 02 D9 36
23 00 02 15 74
23 00 02 3F 74
23 00 02 66 74
23 00 02 8C 74
23 00 02 B4 74
23 00 02 DA 74
23 00 02 16 9F
23 00 02 40 9F
23 00 02 67 9F
23 00 02 8D 9F
23 00 02 B5 9F
23 00 02 DB 9F
23 00 02 17 DC
23 00 02 41 DC
23 00 02 68 DC
23 00 02 8E DC
23 00 02 B6 DC
23 00 02 DC DC
23 00 02 1D FF
23 00 02 19 03
23 00 02 47 FF
23 00 02 43 03
23 00 02 6E FF
23 00 02 6A 03
23 00 02 94 FF
23 00 02 90 03
23 00 02 BC FF
23 00 02 B8 03
23 00 02 E2 FF
23 00 02 DE 03
23 00 02 1A 35
23 00 02 44 35
23 00 02 6B 35
23 00 02 91 35
23 00 02 B9 35
23 00 02 DF 35
23 00 02 1B 45
23 00 02 45 45
23 00 02 6C 45
23 00 02 92 45
23 00 02 BA 45
23 00 02 E0 45
23 00 02 1C 55
23 00 02 46 55
23 00 02 6D 55
23 00 02 93 55
23 00 02 BB 55
23 00 02 E1 55
23 00 02 22 FF
23 00 02 1E 68
23 00 02 4C FF
23 00 02 48 68
23 00 02 73 FF
23 00 02 6F 68
23 00 02 99 FF
23 00 02 95 68
23 00 02 C1 FF
23 00 02 BD 68
23 00 02 E7 FF
23 00 02 E3 68
23 00 02 1F 7E
23 00 02 49 7E
23 00 02 70 7E
23 00 02 96 7E
23 00 02 BE 7E
23 00 02 E4 7E
23 00 02 20 97
23 00 02 4A 97
23 00 02 71 97
23 00 02 97 97
23 00 02 BF 97
23 00 02 E5 97
23 00 02 21 B5
23 00 02 4B B5
23 00 02 72 B5
23 00 02 98 B5
23 00 02 C0 B5
23 00 02 E6 B5
23 00 02 25 F0
23 00 02 23 E8
23 00 02 4F F0
23 00 02 4D E8
23 00 02 76 F0
23 00 02 74 E8
23 00 02 9C F0
23 00 02 9A E8
23 00 02 C4 F0
23 00 02 C2 E8
23 00 02 EA F0
23 00 02 E8 E8
23 00 02 24 FF
23 00 02 4E FF
23 00 02 75 FF
23 00 02 9B FF
23 00 02 C3 FF
23 00 02 E9 FF
23 00 02 FE 3D
23 00 02 00 04
23 00 02 FE 23
23 00 02 08 82
23 00 02 0A 00
23 00 02 0B 00
23 00 02 0C 01
23 00 02 16 00
23 00 02 18 02
23 00 02 1B 04
23 00 02 19 04
23 00 02 1C 81
23 00 02 1F 00
23 00 02 20 03
23 00 02 23 04
23 00 02 21 01
23 00 02 54 63
23 00 02 55 54
23 00 02 6E 45
23 00 02 6D 36
23 00 02 FE 3D
23 00 02 55 78
23 00 02 FE 20
23 00 02 26 30
23 00 02 FE 3D
23 00 02 20 71
23 00 02 50 8F
23 00 02 51 8F
23 00 02 FE 00
23 00 02 35 00
05 78 01 11
05 1E 01 29
];
panel-exit-sequence = [
05 00 01 28
05 00 01 10
];
disp_timings0: display-timings {
native-mode = <&dsi_timing0>;
dsi_timing0: timing0 {
clock-frequency = <132000000>;
hactive = <1080>;
vactive = <1920>;
hfront-porch = <15>;
hsync-len = <2>;
hback-porch = <30>;
vfront-porch = <15>;
vsync-len = <2>;
vback-porch = <15>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi: endpoint {
remote-endpoint = <&dsi_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi>;
};
};
};
};
&dsi_in_vp0 {
status = "okay";
};
&dsi_panel {
power-supply = <&vcc3v3_lcd_n>;
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_rst_gpio>;
};
&gpu {
status = "okay";
mali-supply = <&vdd_gpu>;
};
&i2c2 {
status = "okay";
gt1x: gt1x@14 {
compatible = "goodix,gt1x";
reg = <0x14>;
pinctrl-names = "default";
pinctrl-0 = <&touch_gpio>;
goodix,rst-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
/*
* power-supply should switche to vcc3v3_lcd1_n
* when mipi panel is connected to dsi1.
*/
power-supply = <&vcc3v3_lcd_n>;
};
};
&pinctrl {
lcd {
lcd_rst_gpio: lcd-rst-gpio {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
touch {
touch_gpio: touch-gpio {
rockchip,pins =
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm5 {
status = "okay";
};
&route_dsi {
status = "okay";
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
full-pwr-cycle-in-suspend;
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usbdrd30 {
status = "okay";
};
&usbdrd_dwc3 {
status = "okay";
dr_mode = "otg";
extcon = <&u2phy>;
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
};
&video_phy {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};

575
arch/arm64/boot/dts/rockchip/rk3562-iotest-lp3-v10.dtsi Normal file
View File

@@ -0,0 +1,575 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3562.dtsi"
#include "rk3562-rk809.dtsi"
#include <dt-bindings/display/drm_mipi_dsi.h>
/ {
model = "Rockchip RK3562 IOTEST LP3 V10 Board";
compatible = "rockchip,rk3562-iotest-lp3-v10", "rockchip,rk3562";
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm5 0 25000 0>;
brightness-levels = <
0 20 20 21 21 22 22 23
23 24 24 25 25 26 26 27
27 28 28 29 29 30 30 31
31 32 32 33 33 34 34 35
35 36 36 37 37 38 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255
>;
default-brightness-level = <200>;
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
test-power {
status = "okay";
};
vcc3v3_lcd_n: vcc3v3-lcd0-n {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd_n";
gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc3v3_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
dsm_sound: dsm-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,dsm-sound";
simple-audio-card,bitclock-master = <&sndcodec>;
simple-audio-card,frame-master = <&sndcodec>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&sai1>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&dsm>;
};
};
};
&combphy_pu {
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};
&display_subsystem {
status = "okay";
};
&dsi {
status = "okay";
//rockchip,lane-rate = <1000>;
dsi_panel: panel@0 {
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
backlight = <&backlight>;
reset-delay-ms = <60>;
enable-delay-ms = <60>;
prepare-delay-ms = <60>;
unprepare-delay-ms = <60>;
disable-delay-ms = <60>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
23 00 02 FE 21
23 00 02 04 00
23 00 02 00 64
23 00 02 2A 00
23 00 02 26 64
23 00 02 54 00
23 00 02 50 64
23 00 02 7B 00
23 00 02 77 64
23 00 02 A2 00
23 00 02 9D 64
23 00 02 C9 00
23 00 02 C5 64
23 00 02 01 71
23 00 02 27 71
23 00 02 51 71
23 00 02 78 71
23 00 02 9E 71
23 00 02 C6 71
23 00 02 02 89
23 00 02 28 89
23 00 02 52 89
23 00 02 79 89
23 00 02 9F 89
23 00 02 C7 89
23 00 02 03 9E
23 00 02 29 9E
23 00 02 53 9E
23 00 02 7A 9E
23 00 02 A0 9E
23 00 02 C8 9E
23 00 02 09 00
23 00 02 05 B0
23 00 02 31 00
23 00 02 2B B0
23 00 02 5A 00
23 00 02 55 B0
23 00 02 80 00
23 00 02 7C B0
23 00 02 A7 00
23 00 02 A3 B0
23 00 02 CE 00
23 00 02 CA B0
23 00 02 06 C0
23 00 02 2D C0
23 00 02 56 C0
23 00 02 7D C0
23 00 02 A4 C0
23 00 02 CB C0
23 00 02 07 CF
23 00 02 2F CF
23 00 02 58 CF
23 00 02 7E CF
23 00 02 A5 CF
23 00 02 CC CF
23 00 02 08 DD
23 00 02 30 DD
23 00 02 59 DD
23 00 02 7F DD
23 00 02 A6 DD
23 00 02 CD DD
23 00 02 0E 15
23 00 02 0A E9
23 00 02 36 15
23 00 02 32 E9
23 00 02 5F 15
23 00 02 5B E9
23 00 02 85 15
23 00 02 81 E9
23 00 02 AD 15
23 00 02 A9 E9
23 00 02 D3 15
23 00 02 CF E9
23 00 02 0B 14
23 00 02 33 14
23 00 02 5C 14
23 00 02 82 14
23 00 02 AA 14
23 00 02 D0 14
23 00 02 0C 36
23 00 02 34 36
23 00 02 5D 36
23 00 02 83 36
23 00 02 AB 36
23 00 02 D1 36
23 00 02 0D 6B
23 00 02 35 6B
23 00 02 5E 6B
23 00 02 84 6B
23 00 02 AC 6B
23 00 02 D2 6B
23 00 02 13 5A
23 00 02 0F 94
23 00 02 3B 5A
23 00 02 37 94
23 00 02 64 5A
23 00 02 60 94
23 00 02 8A 5A
23 00 02 86 94
23 00 02 B2 5A
23 00 02 AE 94
23 00 02 D8 5A
23 00 02 D4 94
23 00 02 10 D1
23 00 02 38 D1
23 00 02 61 D1
23 00 02 87 D1
23 00 02 AF D1
23 00 02 D5 D1
23 00 02 11 04
23 00 02 39 04
23 00 02 62 04
23 00 02 88 04
23 00 02 B0 04
23 00 02 D6 04
23 00 02 12 05
23 00 02 3A 05
23 00 02 63 05
23 00 02 89 05
23 00 02 B1 05
23 00 02 D7 05
23 00 02 18 AA
23 00 02 14 36
23 00 02 42 AA
23 00 02 3D 36
23 00 02 69 AA
23 00 02 65 36
23 00 02 8F AA
23 00 02 8B 36
23 00 02 B7 AA
23 00 02 B3 36
23 00 02 DD AA
23 00 02 D9 36
23 00 02 15 74
23 00 02 3F 74
23 00 02 66 74
23 00 02 8C 74
23 00 02 B4 74
23 00 02 DA 74
23 00 02 16 9F
23 00 02 40 9F
23 00 02 67 9F
23 00 02 8D 9F
23 00 02 B5 9F
23 00 02 DB 9F
23 00 02 17 DC
23 00 02 41 DC
23 00 02 68 DC
23 00 02 8E DC
23 00 02 B6 DC
23 00 02 DC DC
23 00 02 1D FF
23 00 02 19 03
23 00 02 47 FF
23 00 02 43 03
23 00 02 6E FF
23 00 02 6A 03
23 00 02 94 FF
23 00 02 90 03
23 00 02 BC FF
23 00 02 B8 03
23 00 02 E2 FF
23 00 02 DE 03
23 00 02 1A 35
23 00 02 44 35
23 00 02 6B 35
23 00 02 91 35
23 00 02 B9 35
23 00 02 DF 35
23 00 02 1B 45
23 00 02 45 45
23 00 02 6C 45
23 00 02 92 45
23 00 02 BA 45
23 00 02 E0 45
23 00 02 1C 55
23 00 02 46 55
23 00 02 6D 55
23 00 02 93 55
23 00 02 BB 55
23 00 02 E1 55
23 00 02 22 FF
23 00 02 1E 68
23 00 02 4C FF
23 00 02 48 68
23 00 02 73 FF
23 00 02 6F 68
23 00 02 99 FF
23 00 02 95 68
23 00 02 C1 FF
23 00 02 BD 68
23 00 02 E7 FF
23 00 02 E3 68
23 00 02 1F 7E
23 00 02 49 7E
23 00 02 70 7E
23 00 02 96 7E
23 00 02 BE 7E
23 00 02 E4 7E
23 00 02 20 97
23 00 02 4A 97
23 00 02 71 97
23 00 02 97 97
23 00 02 BF 97
23 00 02 E5 97
23 00 02 21 B5
23 00 02 4B B5
23 00 02 72 B5
23 00 02 98 B5
23 00 02 C0 B5
23 00 02 E6 B5
23 00 02 25 F0
23 00 02 23 E8
23 00 02 4F F0
23 00 02 4D E8
23 00 02 76 F0
23 00 02 74 E8
23 00 02 9C F0
23 00 02 9A E8
23 00 02 C4 F0
23 00 02 C2 E8
23 00 02 EA F0
23 00 02 E8 E8
23 00 02 24 FF
23 00 02 4E FF
23 00 02 75 FF
23 00 02 9B FF
23 00 02 C3 FF
23 00 02 E9 FF
23 00 02 FE 3D
23 00 02 00 04
23 00 02 FE 23
23 00 02 08 82
23 00 02 0A 00
23 00 02 0B 00
23 00 02 0C 01
23 00 02 16 00
23 00 02 18 02
23 00 02 1B 04
23 00 02 19 04
23 00 02 1C 81
23 00 02 1F 00
23 00 02 20 03
23 00 02 23 04
23 00 02 21 01
23 00 02 54 63
23 00 02 55 54
23 00 02 6E 45
23 00 02 6D 36
23 00 02 FE 3D
23 00 02 55 78
23 00 02 FE 20
23 00 02 26 30
23 00 02 FE 3D
23 00 02 20 71
23 00 02 50 8F
23 00 02 51 8F
23 00 02 FE 00
23 00 02 35 00
05 78 01 11
05 1E 01 29
];
panel-exit-sequence = [
05 00 01 28
05 00 01 10
];
disp_timings0: display-timings {
native-mode = <&dsi_timing0>;
dsi_timing0: timing0 {
clock-frequency = <132000000>;
hactive = <1080>;
vactive = <1920>;
hfront-porch = <15>;
hsync-len = <2>;
hback-porch = <30>;
vfront-porch = <15>;
vsync-len = <2>;
vback-porch = <15>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi: endpoint {
remote-endpoint = <&dsi_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi>;
};
};
};
};
&dsi_in_vp0 {
status = "okay";
};
&dsi_panel {
power-supply = <&vcc3v3_lcd_n>;
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_rst_gpio>;
};
&gpu {
status = "okay";
mali-supply = <&vdd_gpu>;
};
&i2c2 {
status = "okay";
gt1x: gt1x@14 {
compatible = "goodix,gt1x";
reg = <0x14>;
pinctrl-names = "default";
pinctrl-0 = <&touch_gpio>;
goodix,rst-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
/*
* power-supply should switche to vcc3v3_lcd1_n
* when mipi panel is connected to dsi1.
*/
power-supply = <&vcc3v3_lcd_n>;
};
};
&pinctrl {
lcd {
lcd_rst_gpio: lcd-rst-gpio {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
touch {
touch_gpio: touch-gpio {
rockchip,pins =
<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm5 {
status = "okay";
};
&route_dsi {
status = "okay";
};
&sdhci {
bus-width = <8>;
no-sdio;
no-sd;
non-removable;
max-frequency = <200000000>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
full-pwr-cycle-in-suspend;
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usbdrd30 {
status = "okay";
};
&usbdrd_dwc3 {
status = "okay";
dr_mode = "otg";
extcon = <&u2phy>;
snps,dis_u2_susphy_quirk;
snps,usb2-lpm-disable;
};
&video_phy {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};

3
drivers/devfreq/rockchip_dmc.c
View File

@@ -180,7 +180,8 @@ static struct monitor_dev_profile dmc_mdevp = {
static inline unsigned long is_dualview(unsigned long status)
{
return (status & SYS_STATUS_LCDC0) && (status & SYS_STATUS_LCDC1);
return ((status & SYS_STATUS_SINGLEVP) &&
((status & SYS_STATUS_MULTIVP) || (status & SYS_STATUS_EBC)));
}
static inline unsigned long is_isp(unsigned long status)

25
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -2224,12 +2224,21 @@ static enum vop2_wb_format vop2_convert_wb_format(uint32_t format)
}
}
static void vop2_set_system_status(struct vop2 *vop2)
static void vop2_set_system_status(struct vop2 *vop2, bool is_enabled)
{
if (hweight8(vop2->active_vp_mask) > 1)
rockchip_set_system_status(SYS_STATUS_DUALVIEW);
else
rockchip_clear_system_status(SYS_STATUS_DUALVIEW);
unsigned int nports = hweight8(vop2->active_vp_mask);
if (is_enabled) {
if (nports == 2)
rockchip_set_system_status(SYS_STATUS_MULTIVP);
else if (nports == 1)
rockchip_set_system_status(SYS_STATUS_SINGLEVP);
} else {
if (nports == 0)
rockchip_clear_system_status(SYS_STATUS_SINGLEVP);
else if (nports == 1)
rockchip_clear_system_status(SYS_STATUS_MULTIVP);
}
}
static bool vop2_win_rb_swap(uint32_t format)
@@ -4963,7 +4972,7 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
memset(&vp->active_tv_state, 0, sizeof(vp->active_tv_state));
vop2_unlock(vop2);
vop2_set_system_status(vop2);
vop2_set_system_status(vop2, false);
if (!vop2->active_vp_mask)
rockchip_request_early_suspend();
@@ -6960,7 +6969,7 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data)
if (on) {
vp->loader_protect = true;
vop2->active_vp_mask |= BIT(vp->id);
vop2_set_system_status(vop2);
vop2_set_system_status(vop2, true);
vop2_initial(crtc);
if (crtc->primary) {
win = to_vop2_win(crtc->primary);
@@ -8967,7 +8976,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_sta
}
vop2->active_vp_mask |= BIT(vp->id);
vop2_set_system_status(vop2);
vop2_set_system_status(vop2, true);
rockchip_request_late_resume();
vop2_lock(vop2);

32
drivers/media/i2c/techpoint/techpoint_tp9950.c
View File

@@ -23,10 +23,10 @@ static struct techpoint_video_modes supported_modes[] = {
.common_reg_size = 0,
.bpp = TP9950_BITS_PER_SAMPLE,
.lane = TP9950_LANES,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
#endif
#if TP9950_DEF_NTSC
@@ -43,10 +43,10 @@ static struct techpoint_video_modes supported_modes[] = {
.common_reg_size = 0,
.bpp = TP9950_BITS_PER_SAMPLE,
.lane = TP9950_LANES,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
#endif
#if TP9950_DEF_1080P
@@ -64,10 +64,10 @@ static struct techpoint_video_modes supported_modes[] = {
.common_reg_size = 0,
.bpp = TP9950_BITS_PER_SAMPLE,
.lane = TP9950_LANES,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
#endif
#if TP9950_DEF_720P
@@ -84,10 +84,10 @@ static struct techpoint_video_modes supported_modes[] = {
.common_reg_size = 0,
.bpp = TP9950_BITS_PER_SAMPLE,
.lane = TP9950_LANES,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
#endif
};

32
drivers/media/i2c/techpoint/techpoint_tp9951.c
View File

@@ -23,10 +23,10 @@ static struct techpoint_video_modes supported_modes[] = {
.common_reg_size = 0,
.bpp = TP9951_BITS_PER_SAMPLE,
.lane = TP9951_LANES,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
#endif
#if TP9951_DEF_NTSC
@@ -43,10 +43,10 @@ static struct techpoint_video_modes supported_modes[] = {
.common_reg_size = 0,
.bpp = TP9951_BITS_PER_SAMPLE,
.lane = TP9951_LANES,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
#endif
#if TP9951_DEF_1080P
@@ -64,10 +64,10 @@ static struct techpoint_video_modes supported_modes[] = {
.common_reg_size = 0,
.bpp = TP9951_BITS_PER_SAMPLE,
.lane = TP9951_LANES,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
#endif
#if TP9951_DEF_720P
@@ -84,10 +84,10 @@ static struct techpoint_video_modes supported_modes[] = {
.common_reg_size = 0,
.bpp = TP9951_BITS_PER_SAMPLE,
.lane = TP9951_LANES,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
.vc[PAD0] = 0,
.vc[PAD1] = 1,
.vc[PAD2] = 2,
.vc[PAD3] = 3,
},
#endif
};

4
drivers/media/i2c/techpoint/techpoint_v4l2.c
View File

@@ -106,8 +106,8 @@ static int techpoint_analyze_dts(struct techpoint *techpoint)
fwnode = of_fwnode_handle(endpoint);
rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
if (rval <= 0) {
dev_err(dev, " Get mipi lane num failed!\n");
return -EINVAL;
rval = 4;
dev_err(dev, " Get mipi lane num failed!, set default 4\n");
}
techpoint->data_lanes = rval;

8
drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_pcie_linux.c
View File

@@ -87,6 +87,10 @@
#include <dhd_plat.h>
#ifdef CONFIG_ARCH_ROCKCHIP
#include <linux/aspm_ext.h>
#endif
#define PCI_CFG_RETRY 10 /* PR15065: retry count for pci cfg accesses */
#define OS_HANDLE_MAGIC 0x1234abcd /* Magic # to recognize osh */
#define BCM_MEM_FILENAME_LEN 24 /* Mem. filename length */
@@ -2404,6 +2408,10 @@ dhdpcie_start_host_dev(dhd_bus_t *bus)
ret = tegra_pcie_pm_resume();
#endif /* CONFIG_ARCH_TEGRA_210_SOC */
#endif /* CONFIG_ARCH_TEGRA */
#ifdef CONFIG_ARCH_ROCKCHIP
if (bus->rc_dev)
ret = rockchip_dw_pcie_pm_ctrl_for_user(bus->rc_dev, ROCKCHIP_PCIE_PM_CTRL_RESET);
#endif /* CONFIG_ARCH_ROCKCHIP */
if (ret) {
DHD_ERROR(("%s Failed to bring up PCIe link\n", __FUNCTION__));

33
drivers/pci/controller/dwc/pcie-dw-rockchip.c
View File

@@ -21,6 +21,7 @@
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/rfkill-wlan.h>
#include <linux/aspm_ext.h>
#include "pcie-designware.h"
#include "../rockchip-pcie-dma.h"
@@ -1594,6 +1595,38 @@ err:
return ret;
}
int rockchip_dw_pcie_pm_ctrl_for_user(struct pci_dev *dev, enum rockchip_pcie_pm_ctrl_flag flag)
{
struct dw_pcie_rp *pp;
struct dw_pcie *pci;
struct rk_pcie *rk_pcie;
if (!dev || !dev->bus || !dev->bus->sysdata) {
pr_err("%s input invalid\n", __func__);
return -EINVAL;
}
pp = dev->bus->sysdata;
pci = to_dw_pcie_from_pp(pp);
rk_pcie = to_rk_pcie(pci);
switch (flag) {
case ROCKCHIP_PCIE_PM_CTRL_RESET:
rockchip_dw_pcie_suspend(rk_pcie->pci->dev);
rockchip_dw_pcie_resume(rk_pcie->pci->dev);
break;
default:
dev_err(rk_pcie->pci->dev, "%s flag=%d invalid\n", __func__, flag);
return -EINVAL;
}
dev_info(rk_pcie->pci->dev, "%s ltssm=%x\n", __func__,
rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
return 0;
}
EXPORT_SYMBOL(rockchip_dw_pcie_pm_ctrl_for_user);
#ifdef CONFIG_PCIEASPM
static int rockchip_dw_pcie_prepare(struct device *dev)
{

22
drivers/soc/rockchip/rockchip_pm_config.c
View File

@@ -40,7 +40,6 @@ enum rk_pm_state {
RK_PM_STATE_MAX
};
#ifndef MODULE
static const char * const pm_state_str[RK_PM_STATE_MAX] = {
[RK_PM_MEM] = "mem",
[RK_PM_MEM_LITE] = "mem-lite",
@@ -51,7 +50,6 @@ static struct rk_on_off_regulator_list {
struct regulator_dev *on_reg_list[MAX_ON_OFF_REG_NUM];
struct regulator_dev *off_reg_list[MAX_ON_OFF_REG_NUM];
} on_off_regs_list[RK_PM_STATE_MAX];
#endif
/* rk_tag related defines */
#define sleep_tag_next(t) \
@@ -98,7 +96,6 @@ static const struct of_device_id pm_match_table[] = {
{ },
};
#ifndef MODULE
enum {
RK_PM_VIRT_PWROFF_EN = 0,
RK_PM_VIRT_PWROFF_IRQ_CFG = 1,
@@ -107,6 +104,11 @@ enum {
static u32 *virtual_pwroff_irqs;
static inline suspend_state_t get_mem_sleep_current(void)
{
return __is_defined(MODULE) ? PM_SUSPEND_MEM : mem_sleep_current;
}
static int rockchip_pm_virt_pwroff_prepare(struct sys_off_data *data)
{
int error, i;
@@ -265,7 +267,7 @@ static int parse_on_off_regulator(struct device_node *node, enum rk_pm_state sta
const struct rk_sleep_config *rockchip_get_cur_sleep_config(void)
{
suspend_state_t suspend_state = mem_sleep_current;
suspend_state_t suspend_state = get_mem_sleep_current();
enum rk_pm_state state = suspend_state - PM_SUSPEND_MEM;
if (state >= RK_PM_STATE_MAX)
@@ -274,7 +276,6 @@ const struct rk_sleep_config *rockchip_get_cur_sleep_config(void)
return &sleep_config[state];
}
EXPORT_SYMBOL_GPL(rockchip_get_cur_sleep_config);
#endif
static int parse_mcu_sleep_config(struct device_node *node)
{
@@ -535,23 +536,23 @@ static int pm_config_probe(struct platform_device *pdev)
parse_io_config(&pdev->dev);
parse_mcu_sleep_config(node);
#ifndef MODULE
if (__is_defined(MODULE))
return 0;
parse_virtual_pwroff_config(pdev, node);
for (i = RK_PM_MEM; i < RK_PM_STATE_MAX; i++) {
parse_sleep_config(node, i);
parse_on_off_regulator(node, i);
}
#endif
return 0;
}
#ifndef MODULE
static int pm_config_prepare(struct device *dev)
{
int i;
suspend_state_t suspend_state = mem_sleep_current;
suspend_state_t suspend_state = get_mem_sleep_current();
enum rk_pm_state state = suspend_state - PM_SUSPEND_MEM;
struct regulator_dev **on_list;
struct regulator_dev **off_list;
@@ -595,16 +596,13 @@ static int pm_config_prepare(struct device *dev)
static const struct dev_pm_ops rockchip_pm_ops = {
.prepare = pm_config_prepare,
};
#endif
static struct platform_driver pm_driver = {
.probe = pm_config_probe,
.driver = {
.name = "rockchip-pm",
.of_match_table = pm_match_table,
#ifndef MODULE
.pm = &rockchip_pm_ops,
#endif
},
};

4
drivers/soc/rockchip/rockchip_system_monitor.c
View File

@@ -1718,10 +1718,10 @@ static int rockchip_eink_devfs_notifier(struct notifier_block *nb,
{
switch (action) {
case EBC_ON:
rockchip_clear_system_status(SYS_STATUS_LOW_POWER);
rockchip_set_system_status(SYS_STATUS_EBC);
break;
case EBC_OFF:
rockchip_set_system_status(SYS_STATUS_LOW_POWER);
rockchip_clear_system_status(SYS_STATUS_EBC);
break;
default:
break;

3
include/dt-bindings/soc/rockchip-system-status.h
View File

@@ -38,11 +38,14 @@
#define SYS_STATUS_VIDEO_SVEP (1 << 19)
#define SYS_STATUS_VIDEO_4K_60P (1 << 20)
#define SYS_STATUS_DEEP_SUSPEND (1 << 21)
#define SYS_STATUS_EBC (1 << 22)
#define SYS_STATUS_VIDEO (SYS_STATUS_VIDEO_4K | \
SYS_STATUS_VIDEO_1080P | \
SYS_STATUS_VIDEO_4K_10B | \
SYS_STATUS_VIDEO_4K_60P)
#define SYS_STATUS_SINGLEVP SYS_STATUS_LCDC1
#define SYS_STATUS_MULTIVP SYS_STATUS_LCDC0
#define SYS_STATUS_DUALVIEW (SYS_STATUS_LCDC0 | SYS_STATUS_LCDC1)
#define DMC_FREQ_LEVEL_LOW (0x1 << 0)

8
include/linux/aspm_ext.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2022 Rockchip Electronics Co., Ltd. */
/* Copyright (c) 2022-2024 Rockchip Electronics Co., Ltd. */
#ifndef _ASPM_EXT_H
#define _ASPM_EXT_H
@@ -15,4 +15,10 @@ static inline void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_d
static inline bool pcie_aspm_ext_is_in_l1sub_state(struct pci_dev *pdev) { return false; }
#endif
enum rockchip_pcie_pm_ctrl_flag {
ROCKCHIP_PCIE_PM_CTRL_RESET = 1,
};
int rockchip_dw_pcie_pm_ctrl_for_user(struct pci_dev *dev, enum rockchip_pcie_pm_ctrl_flag flag);
#endif