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clk: fractional-divider: Improve fractional divider jitter

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Numerator is greater than 4,the clk jitter is better.

Change-Id: I9fda9ddeb7b26c6b8559b4126e2ad1d29bb850d1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2019-01-24 14:48:33 +08:00
committed by Tao Huang
parent 07e28b187d
commit 49c8309d05
1 changed files with 18 additions and 0 deletions
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18
drivers/clk/clk-fractional-divider.c
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@@ -106,6 +106,24 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
&m, &n);
/*
* When compensation the fractional divider,
* the [1:0] bits of the numerator register are omitted,
* which will lead to a large deviation in the result.
* Therefore, it is required that the numerator must
* be greater than 4.
*/
if (m < 4 && m != 0) {
val = DIV_ROUND_UP(4, m);
n *= val;
m *= val;
if (n > fd->nmask) {
pr_debug("%s n(%ld) is overflow, use mask value\n",
__func__, n);
n = fd->nmask;
}
}
if (fd->lock)
spin_lock_irqsave(fd->lock, flags);
else